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TEA5764UK
FM radio + RDS
Rev. 02 -- 9 August 2005 Product data sheet
1. General description
The TEA5764UK is a single chip electronically tuned FM stereo radio with Radio Data System (RDS) and Radio Broadcast Data System (RBDS) demodulator and RDS/RBDS decoder for portable application with fully integrated IF selectivity and demodulation. The radio is completely adjustment free and only requires a minimum of small and low cost external components. The radio can tune to the European, US and Japanese FM bands. It has a low power consumption and can operate at a low supply voltage.
2. Features
s Chip scale package s High sensitivity due to integrated low noise RF input amplifier s FM mixer for conversion of the US/Europe (87.5 MHz to 108 MHz) and Japanese FM band (76 MHz to 90 MHz) to IF s Preset tuning to receive Japanese TV audio up to 108 MHz s Auto search tuning, raster 100 kHz s RF automatic gain control circuit s LC tuner oscillator operating with low cost fixed chip inductors s Fully integrated FM IF selectivity s Fully integrated FM demodulator; no external discriminator s Crystal oscillator at 32768 Hz, or external reference frequency at 32768 Hz s PLL synthesizer tuning system s IF counter; 7-bit output via the I2C-bus s Level detector; 4-bit level information output via the I2C-bus s Soft mute: signal dependent mute function s Mono/stereo blend: gradual change from mono to stereo, depending on signal s Adjustment-free stereo decoder s Autonomous search tuning function s Standby mode s MPX output s One software programmable port s Fully integrated RDS/RBDS demodulator in accordance with EN50067 s RDS/RBDS decoder with memory for two RDS data blocks provides block synchronization and error correction; block data and status information are available via the I2C-bus s Audio pause detector
Philips Semiconductors
TEA5764UK
FM radio + RDS
s Interrupt flag
3. Applications
s FM stereo radio
4. Quick reference data
Table 1: Electrical parameters general The listed parameters are valid when a crystal is used that meets the requirements as stated in Table 46; All RF input values are defined in potential difference, except when EMF is explicitly stated. Symbol Supplies VCCA ICCA analog supply voltage analog supply current VCCA = 2.5 V to 3.3 V operating mode Standby mode VCCD ICCD digital supply voltage digital supply current VCCD = 2.5 V to 3.3 V operating mode Standby mode Reference voltage VVREFDIG IVREFDIG General fi(FM) Tamb Vsens(EMF) FM input frequency ambient temperature sensitivity EMF value voltage fRF = 76 MHz to 108 MHz; f = 22.5 kHz; fmod = 1 kHz; (S+N)/N = 26 dB; TCdeem = 75 s; A-weighting filter; Baud = 300 Hz to 15 kHz f1 = 200 kHz; f2 = 400 kHz; ftune = 76 MHz to 108 MHz; RFagc = off f1 = 4 MHz; f2 = 8 MHz; ftune = 76 MHz to 108 MHz; RFagc = off ftune = 76 MHz to 108 MHz high-side; f = +200 kHz low-side; f = -200 kHz VVAFL left audio output voltage on pin VAFL VRF = 1 mV; L = R; f = 22.5 kHz; fmod = 1 kHz; no pre-emphasis; TCdeem = 75 s
[1]
Parameter
Conditions
Min 2.5 12 0 2.5 0.3 1 1.65
Typ 2.7 13.7 0.1 2.7 0.7 15 1.8 0.5
Max 3.3 16 1 3.3 1.5 22.5 VCCD 1
Unit V mA A V mA A V A
digital reference voltage for I2C-bus interface digital reference supply current operating mode; VVREFDIG = 1.65 V to VCCD
0
76 -40 -
2.9
108 +85 4.4
MHz C V
FM and RDS overall system parameters
IP3in
in-band 3rd-order intercept point out-of-band 3rd-order intercept point selectivity
78
87
-
dBV
IP3out
87
93
-
dBV
S
39 32 55
43 36 66
75
dB dB mV
TEA5764UK_2
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Product data sheet
Rev. 02 -- 9 August 2005
2 of 64
Philips Semiconductors
TEA5764UK
FM radio + RDS
Table 1: Electrical parameters general The listed parameters are valid when a crystal is used that meets the requirements as stated in Table 46; All RF input values are defined in potential difference, except when EMF is explicitly stated. Symbol VVAFR Parameter right audio output voltage on pin VAFR Conditions VRF = 1 mV; L = R; f = 22.5 kHz; fmod = 1 kHz; no pre-emphasis; TCdeem = 75 s VRF = 1 mV; f = 22.5 kHz; L = R; fmod = 1 kHz; de-emphasis = 75 s; BAF = 300 Hz to 15 kHz; A-weighting filter VRF = 1 mV; f = 67.5 kHz; L = R; fmod = 1 kHz; fpilot = 6.75 kHz; de-emphasis = 75 s; BAF = 300 Hz to 15 kHz; A-weighting filter MST = 0; R = 1 and L = 0 or R = 0 and L = 1; VRF = 30 V; increasing RF input level VRF = 1 mV; f = 75 kHz; fmod = 1 kHz; DTC = 0; Baud = 300 Hz to 15 kHz; A-weighting filter; mono; L = R; no pilot deviation f = 22.5 kHz; fAF = 1 kHz; L = R; SYM1 = 0 and SYM0 = 0; average over 2000 blocks; block quality rate 95 %; fRDS = 2 kHz Min 55 Typ 66 Max 75 Unit mV
(S+N)/N(m) maximum signal-to-noise ratio, mono
54
57
-
dB
(S+N)/N(s)
maximum signal-to-noise ratio, stereo
50
54
-
dB
cs
channel separation
27
33
-
dB
THD
total harmonic distortion
-
0.4
0.9
%
Vsens
RDS sensitivity EMF value
-
17
30
V
[1]
Low-side and high-side selectivity can be measured by changing the mixer LO injection from high-side to low-side.
5. Ordering information
Table 2: Ordering information Package Name TEA5764UK WLB34 Description wafer-level ball grid array; 34 balls; 4 x 4 x 0.36 mm Version TEA5764UK Type number
TEA5764UK_2
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Product data sheet
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Product data sheet Rev. 02 -- 9 August 2005
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. TEA5764UK_2
6. Block diagram
Philips Semiconductors
33 nF 33 nF
GNDA F2 FREQIN G1 XTAL F1
X1 12 pF
GNDD G2
MPXIN G3
MPXOUT VAFL G4 F4
VAFR TMUTE G5 G6
INTCON1 F6
CRYSTAL OSCILLATOR
VCCA E1
3.7
GAIN STABILIZER
TEA5764UK
57 kHz BP FILTER SOFT MUTE SDS
CD3
33 nF
D2
IF FILTER
LIMITER
DEMODULATOR
RDS/RBDS DECODER
G7 INTX
FM antenna
10 nF
LEVEL ADC I/Q MIXER 1st FM /2 N1 IF CENTER FREQUENCY ADJUST AGC
IF COUNT MPX DECODER Iref PAUSE DETECTOR
INTERFACE REGISTER F7 GNDD E6 INTCON2
100 pF 27 pF 47 pF
RFIN1 D1 RFIN2 C1 GNDRF C2 CAGC B1
L1 120 nH
E7 CD2/INTCON3 mono pilot prog. div out ref. div out TUNING SYSTEM I2C-BUS INTERFACE
12 D7 VCCD
D6 GNDD C7 GNDD B7 SDA
MUX VCO A1 LOOPSW
10 nF
SW PORT A3 LO2 A4 CD1 B4 PILLP A5 SWPORT BUSENABLE VREFDIG
47 k
B2 CPOUT
33 nF
A2 LO1
A4
B6
A7 SCL
001aab458
10 k
TEA5764UK
D1
D2
33 nF
33 nF
100 k
L3
L3
FM radio + RDS
33 nF
Fig 1. Block diagram
4 of 64
Philips Semiconductors
TEA5764UK
FM radio + RDS
7. Pinning information
7.1 Pinning
ball A1 index area 1 A B C D E F G
001aac987
TEA5764UK
2 3 4 5 6 7
Transparent top view
Fig 2. Ball configuration TEA5764UK
7.2 Pin description
Table 3: Symbol LOOPSW CPOUT LO1 LO2 CD1 PILLP SWPORT BUSENABLE VREFDIG SCL SDA n.c. GNDD GNDD VCCD CD2/INTCON3 n.c. INTCON2 GNDD INTX n.c. INTCON1
TEA5764UK_2
Pin description Ball A1 B2 A2 A3 A4 B4 A5 A6 B6 A7 B7 C7 D6 D7 E7 E6 F7 G7 F6 Description synthesizer PLL loop filter switch output charge pump output of synthesizer PLL local oscillator coil connection 1 local oscillator coil connection 2 VCO supply decoupling capacitor pilot PLL loop filter software programmable port output I2C-bus enable input digital reference voltage for I2C-bus signals I2C-bus clock line input I2C-bus data line input and output not connected digital ground digital ground digital supply voltage internally connected not connected internally connected; leave open digital ground interrupt flag output not connected internally connected; leave open
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Product data sheet
Rev. 02 -- 9 August 2005
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Philips Semiconductors
TEA5764UK
FM radio + RDS
Pin description ...continued Ball G6 G5 F4 G4 G3 G2 F2 G1 F1 E1 D2 D1 C1 C2 B1 Description soft mute time-constant capacitor right audio output left audio output FM demodulator MPX output MPX decoder and RDS decoder MPX input digital ground; this pin has an internal pull-down resistor of 10 k to ground not connected analog ground not connected 32.768 kHz reference frequency input crystal oscillator input analog supply voltage VCCA decoupling capacitor RF input 1 RF input 2 RF ground RF AGC time-constant capacitor not connected
Table 3: Symbol TMUTE VAFR VAFL MPXOUT MPXIN GNDD n.c. GNDA n.c. FREQIN XTAL VCCA CD3 RFIN1 RFIN2 GNDRF CAGC n.c.
8. Functional description
8.1 Low noise RF amplifier
The LNA input impedance together with the LC RF input circuit defines an FM band filter. The gain of the LNA is controlled by the RF AGC circuit.
8.2 FM I/Q mixer
FM quadrature mixer converts FM RF (76 MHz to 108 MHz) to IF.
8.3 VCO
The varactor tuned LC VCO provides the Local Oscillator (LO) signal for the FM quadrature mixer. The VCO frequency range is 150 MHz to 217 MHz.
8.4 Crystal oscillator
The crystal oscillator can operate with a 32.768 kHz clock crystal. The oscillator can be overridden via the FREFIN pin. When the FREFIN pin is used the oscillator is clocked externally by a 32.768 kHz signal. Selection between a reference clock or a reference crystal can be done via the I2C-bus. When a crystal is connected the FREFIN pin must be left open-circuit, and when pin FREFIN is used a crystal may not be connected. It is not possible to connect a crystal and apply a frequency via the FREFIN pin in the same application.
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Product data sheet
Rev. 02 -- 9 August 2005
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Philips Semiconductors
TEA5764UK
FM radio + RDS
The crystal oscillator generates the reference frequency for the following:
* * * * * *
Reference frequency divider for synthesizer PLL Timing for the IF counter Timing for the pause detector Free running frequency adjustment of the stereo decoder VCO Centre frequency for adjustment of the IF filters Clock frequency of the RDS/RBDS decoder
8.5 PLL tuning system
The PLL synthesizer tuning system is suitable to operate with a 32.768 kHz reference frequency generated by the crystal oscillator or a reference clock of 32.768 kHz fed into the TEA5764UK. To tune the radio to the required frequency requires the PLL word to be calculated and then programmed to the register. The PLL word is 14 bits long; see Table 20 and Table 21. Calculation of this 14-bit word can be done as follows. Formula for high-side injection: 4 x ( f RF + f IF ) N DEC = ------------------------------------f ref Formula for low-side injection: 4 x ( f RF - f IF ) N DEC = ------------------------------------f ref where: NDEC = decimal value of PLL word fRF = wanted tuning frequency (Hz) fIF = intermediate frequency of 225 kHz fREFS = the reference frequency of 32.768 kHz Example for receiving a channel at 100.1 MHz: 4 x ( 100.1 x 10 + 225 x 10 ) N DEC = ----------------------------------------------------------------------- = 12246.704 32768
6 3
(1)
(2)
(3)
The result found using Equation 1 or Equation 2 must always be rounded to the lowest integer value. If rounded down to the lowest integer value of NDEC = 12246, the PLL word becomes 2FD6h. This value can be written to register FRQSETLSB or FRQSETMSB via the I2C-bus and the IC will then either start an autonomous search at this frequency or go to a preset channel at this frequency. When the application is built according to the block diagram shown in Figure 1, and with the preferred components, the PLL will settle to the new frequency within 5 ms. The most accurate tuning is accomplished when a search is followed by a preset to the same frequency.
TEA5764UK_2
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Product data sheet
Rev. 02 -- 9 August 2005
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Philips Semiconductors
TEA5764UK
FM radio + RDS
The PLL is triggered by writing to any one of the bytes FRQSETMSB, FRQSETLSB, TNCTRL1, TNCTRL2, TESTBITS, TESTMODE. Accurate validation of the PLL locking on the new frequency can take 2 ms to 10 ms. When a lock is detected, bit LD is set.
8.6 Band limits
The TEA5764UK can be switched either to the Japanese FM band or to the US/Europe FM band. Setting bit BLIM to logic 0 the band range is 87.5 MHz to 108 MHz; setting bit BLIM to logic 1 selects the Japanese band range of 76 MHz to 90 MHz.
8.7 RF AGC
The RF AGC (or wideband AGC) prevents overloading and limits the amount of intermodulation products created by strong adjacent channels. The RF AGC is on by default and can be turned off via the I2C-bus. The TEA5764UK also has an in-band AGC to prevent overloading by the wanted channel. The in-band AGC is always turned on.
8.8 Local or long distance receive
If bit LDX = 1, the LNA gain is reduced by 6 dB to prevent distortion when a transmitter is very near. If bit LDX = 0, the LNA gain is normal to receive long distance (DX) stations.
8.9 IF filter
A fully integrated IF filter is built-in.
8.10 FM demodulator
The FM quadrature demodulator has an integrated resonator to perform the phase shift of the IF signal.
8.11 IF counter
The received signal is mixed to produce an IF of 225 kHz. The result of the mixing is counted. A good IF count result indicates that the radio is tuned to a valid channel instead of an image or a channel with much interference. The IF counter outputs a 7-bit count result via the I2C-bus. The IF counter is continuously active and can be read at any time via the I2C-bus. It also activates a flag when the IF count result is outside the IF count valid result window; see Section 9.1.4.4. Before a tuning cycle is initiated the IF count period can be set to 2 ms or to 15.6 ms by bit IFCTC. When the IF count period is set to 2 ms, initiating the tuning algorithm with a preset (bit SM = 0) will always give an RDS update as shown in Section 8.22.1. In case the IF count time is set to 15.6 ms, the tuning flowchart illustrated in Figure 3 is used. Once tuned, the IF count period is always 15.6 ms.
TEA5764UK_2
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Product data sheet
Rev. 02 -- 9 August 2005
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Philips Semiconductors
TEA5764UK
FM radio + RDS
8.12 Voltage level generator and analog-to-digital converter
The voltage level indicates the field strength received by the antenna. The voltage level is analog-to-digital converted to a 4-bit word and output via the I2C-bus. The ADC level is continuously active and can be read at any time via the I2C-bus. It also activates a flag when the voltage level falls below a predefined selectable threshold. Bit LHSW allows either large or small hysteresis steps to be chosen; see Table 24 and Section 9.1.4.5. When the ADC level is set to 3, its minimum value, the search algorithm will only stop at channels having a RF level higher than, or equal to, ADC level 3. After completing the search algorithm and being tuned to a station, due to hysteresis the effective limit will be set to 0. This means that the continuous ADC level check will never set the LEVFLAG.
8.13 Mute
8.13.1 Soft mute
The low-pass filtered voltage level drives the soft mute attenuator at low RF input levels: the audio output is faded and hence also the noise (see graphs referenced 1 in Figure 15 and Figure 17). The soft mute function can also be switched off via the I2C-bus, using bit SMUTE.
8.13.2 Hard mute
The audio outputs VAFL and VAFR can be hard-muted by bit MU in byte TNCTRL2, which means that they are put into 3-state. This can also be done by setting bits Left Hard Mute (LHM) or Right Hard Mute (RHM) in byte TESTBITS, which allows either one or both channels to be muted and forces the TEA5764UK to mono mode. When the TEA5764UK is in Standby mode the audio outputs are hard-muted.
8.13.3 Audio frequency mute
The audio signal is muted by setting bit AFM of the TNCTRL1 register to logic 1. In the soft mute attenuator the audio signal is blocked and so pins VAFL and VAFR will be at their DC biasing point with no signal. The audio is automatically muted during an RDS update as shown in the flowchart of Figure 3. When the audio must be muted during Search mode, it is done by setting bit AFM to logic 1 before the search action and resetting it to logic 0 afterwards. Setting bit AFM to logic 0 stops the RDS data.
8.14 MPX decoder
The PLL stereo decoder is adjustment free. It can be switched to mono via the I2C-bus.
8.15 Signal dependent mono/stereo blend (stereo noise cancellation)
If the RF input level decreases, the MPX decoder blends from stereo to mono to limit the output noise. The continuous mono-to-stereo blend can also be programmed via the I2C-bus to an RF level dependent switched mono-to-stereo transition. Stereo noise cancellation can be switched off via the I2C-bus by bit SNC.
TEA5764UK_2
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Product data sheet
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Philips Semiconductors
TEA5764UK
FM radio + RDS
8.16 Software programmable port
One software programmable port (CMOS output) can be addressed via the I2C-bus: Bit SWPM = 1, the software port functions as the output for the FRRFLAG. Bit SWPM = 0, the software port outputs bit SWP of the registers. In Test mode the software port outputs signals according to Table 27. Test mode is selected, setting bit TM of byte TESTMODE to logic 1. The software port cannot be disabled by the PUPD bits; see Section 8.17.
8.17 Standby mode
The radio can be put into Standby mode by the Power-Up / Power-Down (PUPD) bits. The RDS part can be turned off separately or both the RDS and the FM part can be turned off. The TEA5764UK is still accessible via the I2C-bus but takes only a low power from the supply, in Standby mode, the audio outputs are hard-muted.
8.18 Power-on reset
After startup of VCCA and VCCD a power-on reset circuit will generate a reset pulse and the registers will be set to their default values. The power-on reset is effectively generated by VCCD. After a power-on reset the TEA5764UK is in Standby mode and the PUPD bits are set to logic 0. After a power-on reset the registers are reset to their default value, except for byte12R to byte19R and flags DAVFLG, LSYNCFLG and PDFLAG. To reset these, the RDS part must be turned on by setting PUPD. After setting PUPD to logic 1, it will take 0.9 ms to start-up the TEA5764UK and set these registers to their default value. The power supplies can be switched on in any order. When the supply voltage VCCA and VCCD are at 0 V, all I/Os, the audio outputs and the reference clock input are high-ohmic.
8.19 RDS/RBDS
8.19.1 RDS/RBDS demodulator
A fully integrated RDS/RBDS demodulator which uses the reference frequency (32.678 Hz) of the PLL synthesizer tuning system. The RDS demodulator recovers and regenerates the continuously transmitted RDS or RBDS data stream of the multiplex signal (MPXRDS) and provides the signals clock (RDCL), data (RDDA) for further processing by the integrated RDS decoder.
8.19.2 RDS data and clock direct
The RDS demodulator retrieves the RDS data and clock signals, this data can be put directly onto pins VAFL and VAFR by setting bit RDSCDA to logic 1.
TEA5764UK_2
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Product data sheet
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Philips Semiconductors
TEA5764UK
FM radio + RDS
8.19.2.1
RDS/RBDS decoder The RDS decoder provides block synchronization, error correction and flywheel function for reliable extraction of RDS or RBDS block data. Different modes of operation can be selected to fit different application requirements. Availability of new data is signalled by bit DAVFLG and output pin INTX which generates an interrupt. Up to two blocks of data and status information are available via the I2C-bus in a single transmission. The behavior of the DAVFLG is described in Section 10.
8.20 Audio pause detector
The audio pause detector monitors the audio modulation for pauses and responds to low levels. The modulation threshold can be adjusted in 4 steps of 4 dB by control bits PL[1:0]. The minimum time for detecting a pause can be adjusted by control bits PT[1:0] as shown in Table 38. When a pause occurs, flag PDFLAG is set to logic 1 and a hardware interrupt is generated; see Section 9.1.4.6.
8.21 Auto search and Preset mode
In Search mode the TEA5764UK can search channels automatically (see Figure 3).
TEA5764UK_2
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Product data sheet
Rev. 02 -- 9 August 2005
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Philips Semiconductors
TEA5764UK
FM radio + RDS
start
during a preset mute is always active search mode is default not muted unless AHLSI is set
reset flags set PLL frequency
wait for PLL to settle
level OK true
false
set LEVFLAG
IF OK true
false
AHLSI true false
false
search mode true false
search up true increment current_pll by 100 kHz
decrement current_pll by 100 kHz
band limit true BLFLAG = 0 FRRFLAG = 1 no mute BLFLAG = 0 FRRFLAG = 1 mute BLFLAG = 1 FRRFLAG = 1 no mute
false
001aab461
Fig 3. Flowchart auto search or preset
Before starting a search or a preset, the INTMSK register must be reset and only the FRRMSK must be set. This allows the microprocessor to be interrupted only when the search or preset algorithm is ready.
TEA5764UK_2
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Product data sheet
Rev. 02 -- 9 August 2005
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TEA5764UK
FM radio + RDS
8.21.1 Search mode
Search mode is initiated by setting bit SM in byte FRQSETMSB to logic 1. The search direction is set by bit SUD; SUD = 0 (search down), bit SUD = 1 (search up). The tuner starts searching at the frequency set in bytes FRQSETLSB and FRQSETMSB. The Search Stop Level (SSL) bits define the field strength level at which a desired channel is detected. The tuner will stop on a channel with a field strength equal to or higher than this reference level and then checks the IF frequency; when both are valid, the search stops (Note that this depends on bit AHLSI described in Figure 3). If the level check or the IF-count fails, the search continues. If no channels are found, the TEA5764UK stops searching when it has reached the band limit, setting the BLFLAG HIGH. A search always stops when the FRRFLAG is set and on the occurrence of a hardware interrupt, this procedure is shown in Figure 3. The search algorithm can stop at a frequency that is offset from the IF by up to a maximum of 12 kHz. The maximum offset can be limited to 8 kHz by applying a preset. For optimum tuning, it is recommended that a preset is applied after a search and when the found frequency has an offset that is above 8 kHz. After this interrupt the TEA5764UK will not update the tuner registers for a period of 15 ms. The state of the TEA5764UK can be checked by reading the bytes of INTFLAG, FRQCHKMSB, FRQCHKLSB, TNCTRL1 and TNCTRL2. Table 4 shows the possible states of these registers after an auto search.
Table 4: 0 0 0 0 1 1 0 0 1 1 0 0 Tuner truth table [1] 0 1 0 1 0 1 if pin INTX has gone LOW and only IFMSK, FRRMSK and BLMSK were set then this cannot occur channel found during search / preset; FRRMSK set not a valid state a valid channel found and the band limit has been reached during a search; BLMSK or FRRMSK set not a valid state a preset or search has occurred but the wanted channel has a valid RSSI level but fails the IF count when AHLSI was set to logic 1; HLSI must be toggled and a new PLL value must be programmed; FRRMSK set not a valid state band limit is reached during search; no valid channel found; BLMSK or FRRMSK set
IFFLAG BLFLAG FRRFLAG Comment
1 1
[1]
1 1
0 1
This table is valid until 30.6 ms after the tuning cycle has completed. It shows the outcome of the flag register when a read is done after pin INTX goes LOW on condition that no mask bit other than FRRMSK is set.
8.21.2 Preset mode
A preset occurs by setting bit SM to logic 0 and writing a frequency to byte FRQSETMSB. The tuner jumps to the selected frequency and sets the FRRFLAG when it is ready. After this interrupt the TEA5764UK will not update the tuner registers for a period of 15 ms. The state of the TEA5764UK can be checked by reading registers: INTFLAG, FRQCHKLSB, FRQCHKMSB, TNCTRL1 and TNCTRL2. Table 4 shows the possible states after a preset.
TEA5764UK_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 9 August 2005
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Philips Semiconductors
TEA5764UK
FM radio + RDS
8.21.3 Auto high-side and low-side injection stop switch
When a channel is searched or a preset is done, reception can sometimes improve when injection is done at the other side of the wanted channel.
image on low-side
wanted channel
image on high-side
switch LO from high-side to low-side
001aab460
Fig 4. Switch LO from high-side injection to low-side injection using bit HLSI
The TEA5764UK has bit HLSI which toggles the injection of the local oscillator from high-side (bit HLSI = 1) to low-side (bit HLSI = 0). When bit HLSI is toggled, a new PLL setting must be sent to the TEA5764UK. When bit AHLSI is set to logic 1, the search / preset algorithm will stop after a channel has a valid RSSI level check but fails the IF count. The microprocessor can now respond by toggling the HLSI switch and sending a new PLL value to the tuner.
8.21.4 Muting during search or preset
During a preset the tuner is always muted and this is implemented by the algorithm. A search is not muted by default unless bit AFM = 1 or bit AHLSI = 1. When bit AHLSI = 1 and the tuner stopped during a preset or a search because of a wrong IF count, the tuner stays muted; this allows the microprocessor to switch from the high to low setting quietly and wait for the new result. The tuner is always muted if bit AFM = 1 and is independent of a search or a preset. A search can be muted by setting bit AFM to logic 1 before a search is initiated and resetting it to logic 0 when the tuner is ready (only set bit FRRMSK when initiating a search or preset). All these mute actions are done by blocking the audio signal inside the soft mute attenuator, the audio output will keep its DC level and stay low-ohmic i.e. 50 (a hard mute set by bit MU will cause a plop).
8.22 RDS update/alternative frequency jump
A channel which transmits RDS data can have alternative channels which have the same information. These alternative channel frequencies are in the RDS data, so the microprocessor can read the alternative frequencies and store them in a memory. The tuner can perform an RDS update. This is very similar to a preset, but with a 2 ms IF count time. The tuner will jump to the alternative frequency and check the level and the IF count using a 2 ms count time. When the RSSI level check is above the specified level and the IF count result is within the limits, then the tuner will stay at the alternative frequency and stay muted, the microprocessor can now decide what to do. If the alternative frequency is not valid it will jump back to the frequency it came from.
TEA5764UK_2 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 9 August 2005
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Philips Semiconductors
TEA5764UK
FM radio + RDS
The algorithm will finish with the FRRFLAG being set and an interrupt is generated. After this interrupt the TEA5764UK will not measure the IF count for a period of 15 ms. 15 ms after completing a RDS jump, a measurement of the IF count will start and hence the IF count result and the IFFLAG will be updated 30.6 ms after completing the algorithm. The level measurement will start immediately after the tuning algorithm, so the LEVFLAG will be updated 500 s after the algorithm. The state of the TEA5764UK can be checked by reading registers INTFLAG, FRQCHKLSB, FRQCHKMSB, IFCHK and LEVCHK. Table 5 shows the possible states after an auto search, Figure 5 is a flowchart showing how the RDS is updated.
8.22.1 Muting during RDS update
An RDS update (AF jump) is always muted. There are two possibilities for leaving the algorithm:
* The tuner jumps to an alternative frequency which is not valid (according to the
specified SSL limit and fixed IF counter limits) and jumps back, then it will automatically unmute.
* Or the tuner jumps to a valid alternative frequency and stays there. Now it does not
unmute. The microprocessor can unmute or it keeps the tuner muted and can check for the presence of RDS data. The valid way to unmute is to apply a preset to the current frequency (an IF count time of 15.6 ms is used at preset, which gives a more accurate IF count result than the result obtained by the AF jump, where 2 ms is used).
Table 5: 0 0 0 0 1 1 1 1
[1]
RDS update truth table [1] 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 if pin INTX is LOW and only IFMSK, FRRMSK and BLMSK were set then this cannot occur alternative frequency jump successful; radio is tuned to the alternative frequency and stays muted not a valid state not a valid state not a valid state AF jump has occurred but the wanted channel fails the IF count; the PLL will be set back to the old value not a valid state if pin INTX is LOW and only IFMSK, FRRMSK and BLMSK were set then this cannot occur
IFFLAG BLFLAG FRRFLAG Comment
This table is valid until 30.6 ms after an RDS update has completed. It shows the outcome of the flag register when a read is done after pin INTX has gone LOW and on condition that only mask bit FRRMSK is set.
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start set IF count time to 2 ms
activate mute store 'old' PLL setting clear LEVFLAG clear IFFLAG set PLL to AF frequency
wait for PLL to settle
level OK true wait for IF counter
false
set LEVFLAG
IF OK true
false
reset 'old' PLL setting
wait for PLL to settle
FRRFLAG = 1 BLFLAG = 0 keep mute (PLL is AF frequency)
FRRFLAG = 1 BLFLAG = 0 not mute (PLL is old frequency)
001aab462
Fig 5. Flowchart RDS update
9. Interrupt handling
9.1 Interrupt register
The first two bytes of the I2C-bus register contain the interrupt masks and the interrupt flags. A flag is set when it is a logic 1.
Table 6: Bit Symbol Table 7: Bit Symbol
TEA5764UK_2
INTFLAG - byte0R 7 DAVFLG 6 TESTBIT 5 LSYNCFLG 4 IFFLAG 3 LEVFLAG 2 PDFLAG 1 FRRFLAG 0 BLFLAG
INTMSK - byte0W / byte1R 7 DAVMSK 6 5 LSYNCMSK 4 IFMSK 3 LEVMSK 2 PDMSK 1 FRRMSK 0 BLMSK
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The interrupt flag register contains the flags set according to the behavior outlined in Section 9.1.4. When these flags are set they can also cause the INTX to go active (hardware interrupt line) depending on the status of the corresponding mask bit in Table 7. A logic 1 in the mask register enables the hardware interrupt for that flag. Hence, it is conceivable that, with all the mask bits cleared, the software could operate in a continuous polling mode that reads the interrupt flag register for any bits that maybe set. Interrupt mask bits are always cleared after reading the first two bytes of the interrupt register. This is to control multiple hardware interrupts (see Figure 6). Bit LSYNCMSK has a different function and is not cleared after reading the interrupt register bytes, see also Section 9.1.4.3.
9.1.1 Interrupt clearing
The interrupt flag and mask bits are always cleared after:
* They have been read via the I2C-bus * A power-on reset
9.1.2 Timing
The timing sequence for the general operation interrupts is shown in Figure 6 and shows a read access of the interrupt bytes INTFLAG and INTMSK and a subsequent (though not necessarily immediate) write to the mask register. It also indicates the two key timing points A and B. If an interrupt event occurs while the register is being accessed (after point A) it must be held until after the mask register is cleared at the end of the read operation (point B). Point A is after the R/W bit has been decoded and point B is where the acknowledge has been received from the master after the first two bytes have been sent. The LOW time for the INTX line (tLOW) has a maximum value specified in Section 14. However it can be shorter if the read of the INTMSK and INTFLAG bytes occurs within tLOW.
9.1.3 Reset
A reset can be performed at any time by a simple read of the interrupt bytes, byte0R and byte0W, which automatically clears the interrupt flags and masks.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Product data sheet Rev. 02 -- 9 August 2005
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Philips Semiconductors
read access
INTFLAG
INTMSK
write access
INTMSK
FRQSETMSB
FRQSETLSB
data
S
device address
R
A
0R data
A
1R data
A
data
A
S
device address
W
A
0W data
A
1W data
A
2W data
A
P
(2)
interrupt event
(1)
A
B1
B2
interrupt flag bit
(3)
interrupt mask bit
(4) (5)
INTX
(6) (5)
001aab464
(1) Interrupt events that occur outside of the region A-B set their respective flag bits in the normal way immediately and can thus trigger a hardware interrupt if the mask bits are set. (2) The blocking of interrupts is marked by the region A-B1 / B2 depending on the actual read cycle. B1 is when only the INTFLAG is read and a stop condition is received (only INTFLAG is read so only this will be cleared). B2 is when both registers are read and hence cleared and this is terminated by either an acknowledge or stop bit. (3) Interrupt events that occur between A and B set their respective flags after the mask bits are cleared. Which means that in this diagram an interrupt event occurred in period A-B, so after A-B the flag goes to logic 1. (4) All interrupt mask bits are cleared after the interrupt flag and mask bytes are read. (5) Software writes to the mask byte and enables the required mask bits. Any flags currently set will then trigger a hardware interrupt. (6) INTX is set HIGH (inactive) after the interrupt mask bytes are read.
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Fig 6. I2C-bus interrupt sequence, read and write operation
Philips Semiconductors
TEA5764UK
FM radio + RDS
9.1.4 Interrupt flags and behavior
9.1.4.1 Multiple interrupt events If the interrupt mask register bit is set then the setting of an interrupt flag for that bit causes a hardware interrupt (pin INTX goes LOW). If the event occurs again, before the flag is cleared, then this does not trigger any further hardware interrupts until that specific flag is cleared. However, two different events can occur in sequence and generate a sequence of hardware interrupts. A second interrupt can be generated only after the INTMSK byte is read, followed by a write as the first interrupt blocks the input of the INTX one-shot generator. If subsequent interrupts occur within the INTX LOW period then these do not cause the INTX period to extend beyond its specified maximum period (see Section 9.2). 9.1.4.2 Data available flag The DAVFLG is set when a new block of data is received according to the diagrams shown in Section 10 where the different DAV modes are described. Once synchronized, this continues for all subsequent received blocks (dependent on DAV mode) and in the following situations:
* During sync search, in any DAV mode: two valid blocks in the correct sequence
received with BBC < BBL (synchronized).
* During synchronization search in DAVB mode if a valid A(C')-block has been
detected. This mode can be used for fast search tuning (detection and comparison of the PI code contained in the A or C' block.
* If the pre-processor is synchronized and in mode DAVA and DAVB a new block has
been processed. This mode is the standard data processing mode if the decoder is synchronized.
* If the pre-processor is synchronized and in DAVC mode, two new blocks have been
processed.
* If the decoder is synchronized and in any DAV mode, with LSYNCMSK = 0, loss of
synchronization is detected (flywheel loss of synchronization, resulting in a restart of synchronization search). The DAVFLG is reset by a read of RDSLBLSB (byte15R) or RDSPBLSB (byte17R). An interrupt is asserted each time a new block of data is decoded and when bit DAVMSK is set; for details see Section 10. 9.1.4.3 RDS synchronization flag Bit SYNC, Table 29, shows the status of the RDS decoder. If it is a logic 1 then the decoder is synchronized, if it is a logic 0 it is not. The action of the TEA5764UK depends on the status of bit LSYNCMSK in Table 7. If this is set then the loss of synchronization causes bit LSYNCFL to go to logic 1 when synchronization is lost, and a hardware interrupt is asserted. The RDS part of the TEA5764UK is set to idle and waits for the microprocessor to initiate a new synchronization search by setting bit NWSY as described in Table 36.
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If bit LSYNCMSK is 0 and synchronization is lost, the ASIC automatically starts a new synchronization search. It will not generate a hardware interrupt. The microprocessor can wait until the RDS decoder is synchronized again, this will be indicated by the DAVFLG and the SYNC status bit (this requires bit DAVMSK being set). Bit LSYNCFL is reset by a read of the INTMSK byte1R. Bit LSYNCMSK is not reset by a read of byte INTMSK, it must be set or reset by the microprocessor. Resetting it automatically would change the status of the ASIC and cause an automatic synchronization search as described above. How the synchronization is defined is explained in brief in Section 10. 9.1.4.4 IF frequency flag During an automatic frequency search, preset or AF update, the FM part of the TEA5764UK performs a check of the received IF frequency as a measure of the level of interference in the channel received. If an incorrect IF frequency is received, it indicates the presence of either strong interferers or tuning to an image which sets bit IFFLAG in the INTFLAG register. Also a preset to a channel with no signal will result in a wrong IF count value and hence the setting of bit IFFLAG. When a search, preset or AF update is finished, bit FRRFLAG will be set to indicate this and will generate an interrupt. The microprocessor can now read the outcome of the registers which will contain the IF count value and the IFFLAG status of the channel it is tuned to. In the case of an AF update, the IF count value of the alternative frequency will be in the registers and also when it jumps back, because it will then not start a new IF count. 15 ms after the tuning algorithm has completed the IF counter will start a new count. So 30.6 ms after a failed AF update the IF count result will be equal again to that of the channel from where the jump was initiated. 15 ms after the FRRFLAG has been set the IF counter will start to run continuously on the tuned frequency and if the conditions for correct frequency are not met then this sets bit IFFLAG in the interrupt register. When bit IFMSK is set this will also cause an interrupt. Bit IFFLAG is cleared by a read of byte1R, or by starting the tuning algorithm. 9.1.4.5 RSSI threshold flag The voltage level reflects the field strength received by the antenna. The voltage level is analog to digital converted to a 4-bit value and output via the I2C-bus, this 4-bit level value can be compared to a threshold level set by the SSL bits in Table 19 or the LH bits in Table 26. The ADC level (which converts the analog value to digital) can be triggered to convert in either of two ways: 1. During a tuning step, a search, a preset or an AF update, it is triggered by these algorithms and compares the level with the threshold set by bits SSL[1:0]. Bit LEVFLAG is set if the RSSI level drops below the threshold level set by bits SSL[1:0] (see Table 19). The hardware interrupt is only generated if the corresponding mask bit is set.
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2. After a search, a preset or an AF update, the threshold for comparison is switched to the hysteresis level. The hysteresis level is set by the combination of bits SSL[1:0] and bit LHSW; see Table 24. The result is a hysteresis as shown in Table 26. Then the ADC level starts to run automatically and compares the level every 500 s with the hysteresis level. Bit LEVFLAG is set if the RSSI level drops below the threshold level set by bits SSL[1:0] in combination with bit LHSW (see Table 26); the hardware interrupt is only generated if the corresponding mask bit is set. Bit LHSW allows either a small or a large hysteresis to be selected which results in the levels of the left RSSI hysteresis threshold column for bit LHSW = 0 and the right RSSI hysteresis threshold column; see Table 26. When a search or preset is done with the ADC level set to 3 then when the algorithm has finished, the threshold level is set to 0. Hence the LEVFLAG will never be set. Bit LEVFLAG is cleared by a read of the INTMSK byte1R, or by starting the tuning algorithm. 9.1.4.6 Pause detection flag The pause detector monitors the amplitude of the audio signal and starts counting if it drops below the reference level. When the counter reaches the specified count time, a pause is detected and the PDFLAG is set and will generate an interrupt if bit PDMSK is set to logic 1. The PDFLAG operates independently of bit PDMSK and is only active when the RDS decoder is switched on when bit PUPD is set to logic 1 and when the RDS decoder is not idle if synchronization is lost. See Figure 7. When the peak audio level of the (L+R) drops below the threshold level at t1 it counts the duration of the pause. If the pause lasts longer than the value set by the PT bits, bit PDFLAG is set which in turn generates a hardware interrupt (bit PDMSK set to logic 1). The threshold level at t1 is set by the PL bits shown in Table 38. Bit PDFLAG is cleared by a read of byte1R on condition that the read action occurs more than 500 s after receiving the pause interrupt on the INTX line. The circuit should ignore short transients where the audio level momentarily rises above the threshold (at t2). A pause is detected by comparing the amplitude of the audio signal with the reference level selected by the PL bits. The resultant signal PSCO produced by this comparison is sampled at a frequency of 2341 Hz resulting in signal PSCOn. A pause is detected under the conditions given by Equation 4 and Equation 5. { SUM ( 0toN - 1 ) [ PSCOn = 0 ] - 8 x SUM ( 0toN - 1 ) [ PSCOn = 1 ] } > PT x 2341 t pause - 8 x t audio > PT (4) (5)
where N is the number of samples taken over time and PT is the pause time selected by bus bits PT. When a pause is detected, the integrator will be reset. The integrator value cannot be less than zero; therefore if in Equation 4, the value of the second SUM becomes larger than the first SUM, the output of the integrator remains at zero. Suppose that PT = 20 ms, tpause = 16 ms and taudio = 1.5 ms. The pause detector will count according to Equation 5 as shown in Equation 6: 2 x t pause - 8 x t audio = 20 ms 2 x 16 ms - 8 x 1.5 ms = 20 ms
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(6)
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In Equation 6, the pause detector has measured 1 x 16 ms `pause', 8 x 1.5 ms `no pause' and 1 x 16 ms pause. Therefore on average the pause detector has measured 16 ms - 12 ms + 16 ms = 20 ms pause time and hence a pause will be detected. The PSCOn signal goes directly to the software port. The PDFLAG is set by the integrator and goes to the bus. The interrupt line is triggered by the PDFLAG.
+ reference level "PL" [mV] (1) audio signal 0 - reference level "PL" pause PSCO no pause
t1 audio
t2
integrator output
PT x 2341
0
(2) tpause PSCOn taudio tpause
audio present
no audio present PDFLAG
001aac795
tnp(min) > 5 ms. (1) The reference level is defined in kHz, but is internally transformed to mV e.g. 22.5 kHz = 75 mV; 1 kHz = 3.3 mV. (2) The actual PSCO signal behaves as shown in the top diagram, in the bottom diagram it is assumed that all samples are taken at peaks of the audio signal resulting in PSCOn.
Fig 7. Operation and timing of pause detection according to levels set in Table 38
9.1.4.7
Frequency ready flag The frequency ready flag bit is set to logic 1 when the automatic tuning has finished a search, a preset or an RDS AF update. This bit is described in Table 4 and Table 5. The FRRFLAG is cleared by a read of byte1R.
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9.1.4.8
Band limit flag The band limit bit BLFLAG is set to logic 1 when the automatic tuning has detected the end of the tuning band or when the PLL cannot lock on a certain frequency. This bit is described in Table 4 and Table 5. This bit is cleared by reading byte1R.
9.2 Interrupt output
The interrupt line driver is a MOS transistor with a nominal sink current of 680 A, it is pulled HIGH by an 18 k resistor connected to pin VREFDIG. The interrupt line can be connected to one other similar device with an interrupt output and an 18 k pull-up resistor providing a wired OR function. This allows any of the drivers to pull the line LOW by sinking the current. When a flag is set and not masked it generates an interrupt; see Figure 8.
VCCA
(1)
flag
INTX 10 ms read INTMSK write INTMSK
001aab470
< 10 ms read clears INTX
10 ms
< 10 ms
Read INTMSK clears flag, INTMSK and INTX. Write INTMSK enables INTX. When flag is set, the next interrupts are blocked until read / write INTMSK. (1) Flag is set immediately after the reset, because event is still there.
Fig 8. Interrupt line behavior
10. RDS data processing
The RDS demodulator and decoder perform the following operations:
* * * * * * * *
Demodulation of the RDS/RDBS data stream from the MPX signal Symbol decoding Block and group synchronization Error detection and correction Store last and previous data block received with associated ID and error status Set the DAVFLG when new data is received Set the SYNC status bit according to the current synchronization state Set the LSYNCFL flag when synchronization is lost
The RDS decoder can be set to different modes, each meant to look for specific information.
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10.1 DAV-A processing mode
The DAV-A processing mode is the standard processing mode used. In this mode, when a data block has been decoded, it is transferred to the I2C-bus registers. It generates interrupts on the INTX line after every new block of RDS data that has been processed and also sets the DAVFLG; see Figure 9. The DAVFLG is reset by a read of the I2C-bus registers. If a data block is decoded and a new one arrives, pin INTX goes LOW again, the DAVFLG will be set and the last block will be shifted to the previous block and the last decoded block will be put in the last block. This means that all RDS data is still available in the BL and BP registers. When the I2C-bus registers are not read the DAVFLG will not be reset. If a data block is decoded and a new one arrives, pin INTX goes LOW and the last block will be shifted to the previous block and the last decoded block will be put in the last block. This means that all RDS data is still available in the BL and BP registers but must be read. This is indicated by the setting of bit DOVF. If the I2C-bus registers are still not read, data will be lost, except when this read is done within 20 ms after the INTX line has gone LOW and 2 ms before the arrival of a new block. If this read is done at least 2 ms before the arrival of a new block, then BL and BP are read and the data in the decoder buffer is then instantaneously shifted to the BL register. All data is now read and bit DOVF will be reset.
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21.9 ms read BL A1 B1 C1 D1 read BL A2 read BL B2 C2
DAVFLG set on falling edge DAVFLG DAVN = 0, cleared on read BL register INTX tINT_RD < 10 ms t INT_RD 9.98 ms end read intmsk read intflg + RDS on INTX t READ
> 2 ms
9.98 ms
BL register BP register
A1 x
B1 A1
(1)
C1 B1
C1 B1
(2)
D1 C1
(3)
A2 D1
A2 A2
B2 A2
decoder being decoded registers: in the decoder buffer data overflow bit
B1 A1
C1 B1
(1)
D1 C1
A2 D1
(4) (2)
A2 D1
B2 A1
(5)
B2 A2
001aab471
Bit DOVF set when 2 new blocks received in BL and BP registers (1) If there is no read cycle, B1 is placed in the BP register and the new block C1 is now in the BL register. Bit DOVF is set to indicate two blocks available. (2) Data is not transferred to BL register at the end of the read period/clear DOVF, D1 is missed. (3) In order not to lose D1 a read must be performed before D1 enters decoder buffer, thus read finishes within 21 ms after DOVF set to logic 1. (4) DOVF is cleared when the BL register is read. To be of use, DOVF has to be read before BL and BP registers. (5) To prevent DOVF being set again, an extra read of BL must be performed before A2 has been decoded.
Fig 9. DAV-A timing diagram, DAV-A/B: normal
Figure 9 assumes that block synchronization has been achieved and that no other interrupt flags are being set.
10.2 DAV-B processing mode / fast PI search mode
This mode is used, for example, when the receiver has been re-tuned to a new station, and a fast search of the PI code, always contained in the A or C' block, is required. The diagram shown in Figure 10, assumes that the RDS decoder is unsynchronized initially and is performing a synchronization search. During synchronization search the decoder does not set the DAVFLG until a valid A or C' block is detected. If a valid B block is detected immediately, then the decoder is now synchronized and bit SYNC is set to logic 1. In fact, if any 2 good blocks in a valid order are detected, the RDS decoder will synchronize and give an interrupt.
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If for some reason a valid B block was not received then the next valid A or C' block is decoded and the DAVFLG set. The BP and BL registers record the A block history. When the decoder is synchronized, each decoded block will set the DAVFLG (assuming it was reset by a read action) and generate an interrupt.
21.9 ms
B1 bad
C'1 good
D1 bad
A2 bad
B2 good
C2 good
good A or C' block detected DAVFLG
INTX read intmsk sync status bit not synchronized synchronized read BL register
Bus access - read
BL register BP register
x x
C'1 x
C'1 x
C'1 x
B2 C'1
C2 B2
only valid blocks with no errors are counted as good blocks error correction applied according to SYM bits
001aab472
When the number of blocks detected in the order: `bad' `bad' `good' is 2, synchronization is achieved if another good block followed by either 0, 1 or 2 bad blocks and another good block are then received. If the order is 3 bad blocks, no synchronization is achieved and the counters are reset. The number of allowed bad clocks can be set using the BBG bits
Fig 10. DAV-A timing diagram, DAV B: with bad blocks detected during sync search
10.3 DAV-C reduced processing mode
The DAV-C processing mode is very similar to DAV-A mode with the main exception that a data flag is set only after two new blocks are received. Hence the update rate is reduced by half.
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21.9 ms
being decoded
A1
B1
C1
D1
A2
B2
DAVFLG cleared at end read BP register and forced to zero till end read of RDS 4R DAVFLG
t INTX INTX
INTX cleared at end read INTMSK BL register copied to BP register and C1 to BL register
t INT_RD read access (case 1) t read
B1 copied to BL register shortly before C1 decoded
001aab473
Fig 11. Normal DAV-C timing diagram
21.9 ms
A1
B1
C1
D1
A2
B2
instant copy C1 from decoder buffer to BL, and BL to BP just before D1 decoded due to read action BL register BP register D0 C0 A1 D0 C1 A1 D1 C1 A2 D1 instant copy of A2 from decoder buffer to BL, and BL to BP
DAVFLG not cleared as no read performed DAVFLG (case 2) DAVFLG reset when 1st new block would have been copied
DAVFLG set when 2nd new block in decoder buffer
INTX t INTX = 10 ms read access (case 2) no read on INTX so B1 will be lost data overflow bit 2 new blocks have arrived in BL/BP (C1, D1) and a new block (A2) has entered the decoder buffer. Hence, DOVF is set again. To prevent this, an extra read must be performed after reading (a)
001aab474
(a) t read dashed line shows what would happen if no read occurred at (a). DOVF bit set until the next read of BP register, however D1, A2 would be lost
Fig 12. DAV-C timing diagram, late read of BL, BP register
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10.4 Synchronization
10.4.1 Conditions for synchronization
When the RDS decoder is turned on it must be synchronized to extract valid data from the MPX signal. To do so the decoder automatically initiates a search for synchronization. The conditions to meet synchronization and the status of this synchronization can be set and checked by the following bits:
* BBL (Bad Blocks Lose): these bits can be set via the I2C-bus and have a value
between 0 to 63
* GBL (Good Blocks Lose): these bits can be set via the I2C-bus and have a value
between 0 to 63
* BBG (Bad Blocks Gain): these bits can be set via the I2C-bus and have a value
between 0 to 32
* GBC (Good Block Count): these bits can be read via the I2C-bus and have a value
between 0 to 63
* BBC (Bad Block Count): these bits can be read via the I2C-bus and have a value
between 0 to 63 When the decoder is not synchronized it will initiate a synchronization search. This involves calculation of the syndrome for each block of 26 received bits on a bit-by-bit basis. When a correct syndrome (and hence block ID) is received the decoder clocks the next 26 bits into the internal registers and performs a second syndrome check. Synchronization is found when a certain number of blocks have been decoded and two good blocks have been found, this number of blocks is defined by the BBG bits. If the first block needed for synchronization has been found and the expected second block (after 26 bits) is an invalid block, then the decoder module internal bad_blocks_counter is incremented and the next expected block is calculated; exception: if RBDS mode is selected and the first block is E, then the next expected block is always block A, until synchronization is found or the maximum bad_blocks_counter value is reached. If the decoder module internal bad_blocks_counter reaches the value of BBG[4:0], then a new synchronization search (bit-by-bit) is started immediately to find a new first block. The synchronization is monitored by two flywheel counters, GBC and BBC. These are 6-bit counters that can be preset by bits GBL and BBL to values between 0 and 63. Each time a block is decoded and recognized as a bad block the Bad Block Counter value, BBC, is incremented by 1. When the BBC value is equal to the BBL value, synchronization is lost. Bit SYNC will become 0 and bit LSYNCFL is set to indicate the loss of synchronization. The TEA5764UK will now automatically initiate a new synchronization search. Each time a good block is decoded, the GBC value is incremented. When the GBC value is equal to the GBL value, both counters, BBC and GBC, are set to 0 and a new count starts. The GBC counter is only incremented when the decoder is synchronized.
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FM radio + RDS
10.4.2 Data overflow
During synchronization, after RDS data is read from the registers, new available blocks are shifted to the registers as described in Section 10.1 to Section 10.3. If the registers are not read in time, the decoder cannot shift any new available block to the registers and hence a data overflow will occur, this is indicated by bit DOVF which is set to 1. Bit DOVF is reset by a read of the registers or if bit NWSY = 1 which results in the start of a new synchronization search. Each time when a RDS data block is decoded, bit DAVN goes to logic 0 to indicate the presence of a new data block. Bit DAVN also triggers the interrupt output INTX. In principle the microprocessor must now start reading and must have read all RDS data (byte12R to byte19R) before the arrival of a new RDS data block. In the application it is possible that there is too large a delay between the arrival of a new block and reading this block. This can have various causes such as a microprocessor that has to start-up from Sleep mode or when polling is used instead of interrupt based read actions. Figure 13 shows the behavior of bit DAVFLG and bit DAVN when polling, where reading can occur at any time. Note: Bit DAVN sets the INTX oneshot generator when DAVMSK = 1. Unlike INTX, bit DAVN is not cleared by a read of the mask register.
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10.5 RDS flag behavior during read action
Product data sheet Rev. 02 -- 9 August 2005 30 of 64
TEA5764UK_2
Philips Semiconductors
RDS data A
B
C
D
A
10 ms
B
C
DAVN
(1)
DAVFLG
reset of DAVFLG Read byte: 0R 15R 19R 0W (2) (3) 17R 0R 15R 19R 0W (4) 17R 0R 15R 19R 0W 17R 0R 15R 19R 0W 17R 0R 15R 19R 0W 17R 0R 15R 19R 0W 17R
001aab475
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Blocking DAVFLG: at end of reading byte15R or byte17R (DAV-A, B/C) DAVFLG is forced to zero. Only after reading byte19R DAVFLG is released again. If synchronous reading is performed using ASIC generated interrupts, this problem does not occur. To prevent undefined situations, byte12R to byte19R should always be read in one action immediately after each other. Signal DAVN INTX. (1) Normally reading byte19R would reset bit DAVN, but now it is reset after 10 ms, the maximal LOW time of bit DAVN. (2) Read of byte15R in DAV-A and DAV-B mode clears DAVFLG. In DAV-C mode two consecutive RDS data blocks are read and hence DAVFLG is reset after reading byte17R instead of byte15R (dotted line). (3) Read of byte19R clears bit DAVN. (4) Write byte0W (interrupt register).
TEA5764UK
FM radio + RDS
Fig 13. RDS flag behavior
Philips Semiconductors
TEA5764UK
FM radio + RDS
10.6 Error detection and reporting
The TDA5764UK must report information on the number of errors corrected in the last and previously decoded blocks. This is reported in bits ELB and EPB as shown in Table 29. During synchronization search the error correction is disabled for detection of the first block and is enabled for processing of the second block according to the mode set by the SYM bits as described in Table 36.
10.7 RDS test modes
In Test mode the raw RDS clock and RDS data can be recovered directly from pins VAFL and VAFR when bit RDSCDA = 1.
10.8 Reading RDS data from the registers
To read RDS data the microprocessor must read byte12R to byte19R. All 8 bytes must be read to reset the status bytes 12R and 13R, i.e. effectively the status bits can be updated by the decoder after reading the last bit of byte19R. Bit DOVF is cleared after reading the last bit of byte19R and the status of bit SYNC does not depend on reading the register, bit SYNC indicates if the decoder is synchronized or not. When starting a read action from byte12R, the decoder blocks updates from the RDS bytes until byte19R has been read. RDS byte12R to byte19R must be read in one read action.
11. I2C-bus interface
The I2C-bus interface is based on "The I2C-bus specification", version 2.1 January 2000, expanded by the following definitions.
11.1 Write and read mode
Table 8: S START I2C-bus FM write mode Byte 1 chip address 0010 000 Table 9: S START 0 As Byte 2 xxxx xxxx As Byte n As Byte 8 xxxx xxxx As ACK P STOP R/W ACK byte0W ACK ..... ACK byte6W
I2C-bus RDS write mode Byte 1 chip address 0010 001 As Byte 2 Am Byte n As Byte 8 As non ACK P STOP R/W ACK byte7W 0 xxxx xxxx ACK ..... ACK byte10W xxxx xxxx
When writing all bytes, byte0W to byte10W can be written with one write action.
Table 10: S START I2C-bus FM read mode Byte 1 chip address 0010 000 As Byte 2 Am Byte n Am Byte 17 NAm non ACK P STOP R/W ACK byte0R 1 xxxx xxxx ACK ..... ACK byte15R xxxx xxxx
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FM radio + RDS
Table 11: S START
I2C-bus RDS read mode Byte 1 chip address 0010 001 As Byte 2 Am Byte n Am Byte 17 NAm non ACK P STOP R/W ACK byte12R 1 Table 12: Label S Byte 1 As Byte 2, etc. P Am NAm NA xxxx xxxx I2C-bus transfer description Definition START condition I2C-bus chip address (7 bits) R/W = 0 for write action and R/W = 1 for read action acknowledge from slave TEA5764UK (SDA is LOW) data byte (8 bits) STOP condition acknowledge from master microcontroller (SDA is LOW) non acknowledge from master microcontroller (SDA is HIGH) non acknowledge (SDA is HIGH) ACK ..... ACK byte27R xxxx xxxx
When the TEA5764UK is addressed by the FM radio address, the RDS part (byte12R to byte27R) can be read in one read action. A read does not have to stop at byte11R. Therefore, by effectively only using the RDS part of the address, ignores some bytes which reduces I2C-bus access.
11.2 Data transfer
Structure of the I2C-bus:
* * * *
Slave transceiver Subaddresses not used Maximum LOW-level input voltage: VIL = 0.3 x VVREFDIG Minimum HIGH-level input voltage: VIH = 0.7 x VVREFDIG
Remark: The I2C-bus operates at a maximum clock rate of 400 kHz. It is not allowed to connect the TEA5764UK to a I2C-bus operating at a higher clock rate. Data transfer to the IC:
* Bit 7 of each byte is considered the MSB and has to be transferred as the first bit of
the byte
* The LSB indicates the write or read action * The data becomes valid byte-wise at the appropriate falling edge of the SCL clock * A STOP condition after any byte can shorten transmission times. When writing to the
transceiver by using the STOP condition before completion of the whole transfer: - The remaining bytes will contain the old information - If the transfer of a byte is not completed the new bits will be used, but a new tuning cycle will not be started
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TEA5764UK
FM radio + RDS
To speed up RDS traffic it is possible to read all the RDS data and then only write back byte INTMSK to set the appropriate mask(s) again. I2C-bus activity:
* With bits PUPD the TEA5764UK can be switched in a low current Standby mode. The
I2C-bus is then still active
* When the I2C-bus interface is deactivated, by making pin BUSENABLE LOW and
without programmed Standby mode, the TEA5764UK keeps its normal operation, but is isolated from the I2C-bus lines
* It is possible to operate the TEA5764UK with BUSENABLE hard wired to pin
VREFDIG, and have the bus interface always active.
SDA tf tr
t BUF
SCL P S t HD;STA t SU;BUSEN BUS ENABLE
001aac796
Sr t SU;STO t SU;DAT t HD;DAT t HIGH t LOW t SU;STA t HO;BUSEN
P
tf = fall time of both SDA and SCL signals: 20 + 0.1 Cb < tf < 300 ns, where Cb = total capacitance on bus line in pF. tr = rise time of both SDA and SCL signals: 20 + 0.1 Cb < tf < 300 ns, where Cb = total capacitance on bus line in pF. tHD;STA = hold time (repeated) START condition. After this period, the first clock pulse is generated: > 600 ns. tHIGH = HIGH period of the SCL clock: > 600 ns. tSU;STA = setup time for a repeated START condition: > 600 ns. tHD;DAT = data hold time: 300 < tHD;DAT < 900 ns. Remark: 300 ns lower limit is added because the ASIC has no internal hold time for the SDA signal. tSU;DAT = data setup time: tSU;DAT > 100 ns. If ASIC is used in a standard mode I2C-bus system, tSU;DAT > 250 ns. tSU;STO = setup time for STOP condition: > 600 ns. tBUF = bus free time between a STOP and a START condition: > 600 ns. Cb = capacitive load of one bus line: < 400 pF. tSU;BUSEN = bus enable setup time: tSU;BUSEN > 10 s. tHO;BUSEN = bus enable hold time: tHO:BUSEN > 10 s.
Fig 14. Bus timing diagram
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FM radio + RDS
11.3 Register map
Table 13: Byte Read 0R 1R 2R 3R 4R 5R 6R 7R 8R 9R 10R 11R 12R 13R 14R 15R 16R 17R 18R 19R 20R 21R 22R 23R 24R 25R 26R 27R 7W 8W 9W 10W 5W 6W 0W 1W 2W 3W 4W Write INTFLAG INTMSK FRQSETMSB FRQSETLSB TNCTRL1 TNCTRL2 FRQCHKLSB IFCHK LEVCHK TESTBITS TESTMODE RDSSTAT1 RDSSTAT2 RDSLBMSB RDSLBLSB RDSPBMSB RDSPBLSB RDSBBC RDSGBC RDSCTRL1 RDSCTRL2 PAUSEDET RDSBBL MANID1 MANID2 CHIPID1 CHPID2 R R/W R/W R/W R/W R/W R R R R/W R/W R R R R R R R R R/W R/W R/W R/W R R R R 00 00 80 00 08 D2 00 00 00 10 00 00 50 2B 57 64 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Register overview Byte name Access Reset value Reference
FRQCHKMSB R
11.4 Byte description
Table 14: Bit 7 6 5 4 INTFLAG - byte0R description Symbol DAVFLG TESTBIT LSYNCFL IFFLAG Access R R R R Reset 0 0 0 0 Functional description 1 = RDS data is available internal use 1 = synchronization is lost 1 = IF count is not correct
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FM radio + RDS
INTFLAG - byte0R description ...continued Symbol LEVFLAG Access R Reset 0 Functional description continuous checking of the RSSI level 1 = RSSI level has dropped below (VSSL[1:0] - Vhys) during a tuning period (preset or search) 1 = RSSI level has dropped below VSSL[1:0]
Table 14: Bit 3
2 1 0
PDFLAG FRRFLAG BLFLAG
R R R
0 0 0
1 = pause is detected 1 = tuner state machine is ready 1 = during a search the band limit has been reached or time out
Table 15: Bit 7 6 5 4 3 2 1 0 Table 16: Bit 7 6 5 4 3 2 1 0
INTMSK - byte1R and byte0W description Symbol DAVMSK LSYMSK IFMSK LEVMSK PDMSK FRMSK BLMSK Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Functional description masks bit DAVFLG reserved masks bit LSYNCFL masks bit IFFLAG masks bit LEVFLAG masks bit PDFLAG masks bit FRRFLAG masks bit BLFLAG
FRQSETMSB - byte2R and byte1W description Symbol SUD SM FR13 FR12 FR11 FR10 FR09 FR08 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 0 0 0 0 0 0 0 Functional description 1 = search up 0 = search down 1 = Search mode 0 = Preset mode PLL frequency set bits; see Section 8.5
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FM radio + RDS
FRQSETLSB - byte3R and byte2W description Symbol FR07 FR06 FR05 FR04 FR03 FR02 FR01 FR00 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Functional description PLL frequency set bits; see Section 8.5
Table 17: Bit 7 6 5 4 3 2 1 0 Table 18: Bit 7 and 6
TNCTRL1 - byte4R and byte3W description Symbol PUPD[1:0] Access R/W Reset 00 Functional description power-up and power-down 00 = FM off and RDS off 01 = FM on and RDS off 10 = not used 11 = FM on and RDS on
5
BLIM
R/W
0
1 = Japan FM band 76 MHz to 90 MHz 0 = US / Europe FM band 87.5 MHz to 108 MHz
4 3 2 1 0
SWPM IFCTC AFM SMUTE SNC
R/W R/W R/W R/W R/W
0 1 0 0 0
1 = software port is output of FRRFLAG 0 = SWP 1 = IF count time = 15.02 ms 0 = IF count time = 2.02 ms 1 = left and right audio muted 0 = audio not muted 1 = soft mute on 0 = soft mute off 1 = stereo noise cancellation on 0 = stereo noise cancellation off
Table 19: Bit 7 6 and 5
TNCTRL2 - byte5R and byte4W description Symbol MU SSL[1:0] Access R/W R/W Reset 1 10 Functional description 1 = left and right audio hard-muted 0 = no hard mute search stop level 00 = ADC3 01 = ADC5 10 = ADC7 11 = ADC10
4
HLSI
R/W
1
1 = high-side injection 0 = low-side injection
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FM radio + RDS
TNCTRL2 - byte5R and byte4W description ...continued Symbol MST SWP DTC AHLSI Access R/W R/W R/W R/W Reset 0 0 1 0 Functional description 1 = forced mono 0 = stereo on 1 = pin SWPORT is HIGH 0 = pin SWPORT is LOW 1 = de-emphasis time constant = 50 s 0 = de-emphasis time constant = 75 s see Section 8.21.3 for the functionality of this bit
Table 19: Bit 3 2 1 0
Table 20: Bit 7 and 6 5 4 3 2 1 0 Table 21: Bit 7 6 5 4 3 2 1 0 Table 22: Bit 7 6 5 4 3 2 1 0
FRQCHKMSB - byte6R description Symbol PLL13 PLL12 PLL11 PLL10 PLL09 PLL08 Access R R R R R R Reset Functional description reserved output frequency MSB output frequency output frequency output frequency output frequency output frequency
FRQCHKLSB - byte7R description Symbol PLL07 PLL06 PLL05 PLL04 PLL03 PLL02 PLL01 PLL00 Access R R R R R R R R Reset Functional description output frequency output frequency output frequency output frequency output frequency output frequency output frequency output frequency LSB
IFCHK - byteR8 description Symbol IF6 IF5 IF4 IF3 IF2 IF1 IF0 Access R R R R R R R Reset Functional description IF count MSB IF count IF count IF count IF count IF count IF count LSB reserved
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FM radio + RDS
LEVCHK - byte9R description Symbol LEV3 LEV2 LEV1 LEV0 LD STEREO Access R R R R R R Reset Functional description level count MSB level count bit level count bit level count LSB 1 = PLL is locked 0 = PLL is not locked 1 = pilot detected [1] 0 = no pilot detected reserved
Table 23: Bit 7 6 5 4 3 2 1 and 0
[1]
This bit does not switch the radio to mono or stereo, this depends on the RF input level as shown in sections `Mono stereo blend' or `mono stereo switched' in Table 46.
Table 24: Bit 7 6 5
TESTBITS - byte10R and byte5W description Symbol LHM RHM RDSCDA Access R/W R/W R/W Reset 0 0 0 Functional description 1 = left audio output is hard muted 0 = left audio output is not hard muted 1 = right audio output is hard muted 0 = right audio output is not hard muted 1 = pin VAFL is RDS clock and pin VAFR is RDS data 0 = normal operation 1 = level hysteresis is large 0 = level hysteresis is small 1 = reference frequency selected pin FREQIN 0 = crystal as reference pin XTAL 1 = local DX on, -6 dB gain of LNA 0 = local DX off, LNA has normal gain 1 = RFAGC off 0 = RFAGC on when this bit is set to logic 1 an interrupt is generated on pin INTX
4 3
LHSW TRIGFR
R/W R/W
0 0
2 1 0
LDX RFAGC INTCTRL
R/W R/W R/W
0 0 0
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FM radio + RDS
TESTMODE - byte11R and byte6W description Symbol TM Access R/W R/W Reset 0 0 Functional description reserved 1 = oscillator output and programmable divider output are enabled 0 = normal operation test bits: Table 27 describes selection of signals output to the SWPORT when SWPM = 0; when TM = 1; TB[3:0] = 0; which effectively is an AND function.
Table 25: Bit 7 to 5 4
3 2 1 0 Table 26:
TB3 TB2 TB1 TB0
R/W R/W R/W R/W
0 0 0 0
LH - RSSI level hysteresis RSSI hysteresis threshold LHSW = 0 LHSW = 1 0 1 3 5 0 2 4 7 Test bits (SWPM = 0) TB1 0 0 1 1 0 0 1 1 0 0 1 1 0 TB0 0 1 0 1 0 1 0 1 0 1 0 1 0 SWPORT output signal bit SWP of byte4W, depending on bits SWPM and SWP oscillator output 32.768 kHz; when TM = 1 lock detect bit LD stereo bit STEREO programmable divider; when TM = 1 PSCOn; see Section 9.1.4.6 57 kHz clock 3-state output of RDS comparator reserved reserved reserved reserved 0 0 0 0 1 1 1 1 0 0 0 0 1
RSSI ADC search stop level 3 5 7 10 Table 27: TB3 0 0 0 0 0 0 0 0 1 1 1 1 1
TB2
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FM radio + RDS
RDSSTAT1 - byte12R description Symbol BLID[2:0] Access R Reset Functional description reserved block ID of last block 000 = A 001 = B 010 = C 011 = D 100 = C' 101 = E 110 = invalid block E (RBDS) 111 = invalid block
Table 28: Bit 7 6 to 4
3 and 2 1 to 0
ELB[1:0]
R
-
reserved number of errors for last processed block 00 = no errors 01 = maximum 2 bits 10 = maximum 5 bits 11 = uncorrectable
Table 29: Bit 7 to 5
RDSTAT2 - byte13R description Symbol BPID[2:0] Access R Reset Functional description block ID of previous block 000 = A 001 = B 010 = C 011 = D 100 = C' 101 = E 110 = invalid block E (RBDS) 111 = invalid block
4 and 3
EPB[1:0]
R
-
number of errors for previous processed block 00 = no errors 01 = maximum 2 bits 10 = maximum 5 bits 11 = uncorrectable
2 1 0
SYNC RSTD DOVF
R R R
-
1 = RDS bitstream is synchronized 0 = not synchronized 1 = power-on reset detected 0 = no power-on reset detected 1 = data overflow occurred during read operation 0 = normal operation
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RDSRLBMSB - byte14R description Symbol BL15 BL14 BL13 BL12 BL11 BL10 BL9 BL8 Access R R R R R R R R Reset Functional description last RDS data byte - MSB last RDS data byte last RDS data byte last RDS data byte last RDS data byte last RDS data byte last RDS data byte last RDS data byte
Table 30: Bit 7 6 5 4 3 2 1 0 Table 31: Bit 7 6 5 4 3 2 1 0 Table 32: Bit 7 6 5 4 3 2 1 0 Table 33: Bit 7 6 5 4 3 2 1 0
TEA5764UK_2
RDSLBLSB - byte15R description Symbol BL7 BL6 BL5 BL4 BL3 BL2 BL1 BL0 Access R R R R R R R R Reset Functional description last RDS data byte last RDS data byte last RDS data byte last RDS data byte last RDS data byte last RDS data byte last RDS data byte last RDS data byte - LSB
RDSPBMSB - byte16R description Symbol BP15 BP14 BP13 BP12 BP11 BP10 BP9 BP8 Access R R R R R R R R Reset Functional description previous RDS data byte - MSB previous RDS data byte previous RDS data byte previous RDS data byte previous RDS data byte previous RDS data byte previous RDS data byte previous RDS data byte
RDSPBLSB - byte17R description Symbol BP7 BP6 BP5 BP4 BP3 BP2 BP1 BP0 Access R R R R R R R R Reset Functional description previous RDS data byte previous RDS data byte previous RDS data byte previous RDS data byte previous RDS data byte previous RDS data byte previous RDS data byte previous RDS data byte - LSB
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FM radio + RDS
RDSBBC - byte18R description Symbol BBC5 BBC4 BBC3 BBC2 BBC1 BBC0 GBC5 GBC4 Access R R R R R R R R Reset Functional description bad block count MSB bad block count bad block count bad block count bad block count bad block count LSB good block count MSB good block count
Table 34: Bit 7 6 5 4 3 2 1 0 Table 35: Bit 7 6 5 4 3 to 0 Table 36: Bit 7 6 and 5
RDSGBC - byte19R description Symbol GBC3 GBC2 GBC1 GBC0 Access R R R R Reset Functional description good block count good block count good block count good block count LSB reserved
RDSCTRL1 - byte20R and byte7W description Symbol NWSY SYM[1:0] Access R/W R/W Reset 0 00 Functional description 1 = start new synchronization 0 = normal processing error correction 00 = no correction 01 = maximum 2 bits 10 = maximum 5 bits 11 = no correction
4 3 and 2
RBDS DAC[1:0]
R/W R/W
0 00
1 = RBDS processing mode 0 = RDS processing mode RDS data output mode 00 = DAVA 01 = DAVB 10 = DAVC 11 = not used
1 and 0
-
-
-
reserved
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FM radio + RDS
RDSCTRL2 - byte21R and byte8W description Symbol BBG4 BBG3 BBG2 BBG1 BBG0 Access R/W R/W R/W R/W R/W Reset 1 0 0 0 0 Functional description reserved bad blocks gain MSB bad blocks gain bad blocks gain bad blocks gain bad blocks gain LSB
Table 37: Bit 7 to 5 4 3 2 1 0 Table 38: Bit 7 and 6
PAUSEDET - byte22R and byte9W description Symbol PT[1:0] Access R/W Reset 00 Functional description pause time 00 = 20 ms 01 = 40 ms 10 = 80 ms 11 = 160 ms
5 and 4
PL[1:0]
R/W
00
pause level L = R 00 = 1 kHz 01 = 1.6 kHz 10 = 2.5 kHz 11 = 4.0 kHz
3 2 1 0 Table 39: Bit 7 6 5 4 3 2 1 0
GBL5 GBL4 GBL3 GBL2
R/W R/W R/W R/W
0 0 0 0
number of good blocks lose MSB number of good blocks lose number of good blocks lose number of good blocks lose
RDSBBL - byte23R and byte10W description Symbol GBL1 GBL0 BBL5 BBL4 BBL3 BBL2 BBL1 BBL0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Functional description number of good blocks lose number of good blocks lose LSB number of bad blocks lose MSB number of bad blocks lose number of bad blocks lose number of bad blocks lose number of bad blocks lose number of bad blocks lose LSB
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FM radio + RDS
MANID1 - byte24R description Symbol Access Reset 0 1 0 1 0 0 0 0 Functional description version code MSB version code version code version code LSB manufacturer ID code MSB manufacturer ID code manufacturer ID code manufacturer ID code VERSION3 R VERSION2 R VERSION1 R VERSION0 R MANID10 MANID9 MANID8 MANID7 R R R R
Table 40: Bit 7 6 5 4 3 2 1 0 Table 41: Bit 7 6 5 4 3 2 1 0
MANID2 - byte25R description Symbol MANID6 MANID5 MANID4 MANID3 MANID2 MANID1 MANID0 IDAV Access R R R R R R R R Reset 0 0 1 0 1 0 1 1 Functional description manufacturer ID code manufacturer ID code manufacturer ID code manufacturer ID code manufacturer ID code manufacturer ID code manufacturer ID code LSB 1 = manufacturer ID available 0 = no manufacturer ID available
Table 42: Bit 7 6 5 4 3 2 1 0
CHIPID1 - byte26R description Symbol CHIP ID15 CHIP ID14 CHIP ID13 CHIP ID12 CHIP ID11 CHIP ID10 CHIP ID9 CHIP ID8 Access R R R R R R R R Reset 0 1 0 1 0 1 1 1 Functional description chip identification code MSB chip identification code chip identification code chip identification code chip identification code chip identification code chip identification code chip identification code
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CHIPID2 - byte27R description Symbol CHIP ID7 CHIP ID6 CHIP ID5 CHIP ID4 CHIP ID3 CHIP ID2 CHIP ID1 CHIP ID0 Access R R R R R R R R Reset 0 1 1 0 0 1 0 0 Functional description chip identification code chip identification code chip identification code chip identification code chip identification code chip identification code chip identification code chip identification code LSB
Table 43: Bit 7 6 5 4 3 2 1 0
12. Limiting values
Table 44: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VLO1 VLO2 VCCD VCCA VI/O(n) Tstg Tamb Vesd Parameter VCO tuned circuit output 1 VCO tuned circuit output 2 digital supply voltage analog supply voltage voltage on all inputs and outputs storage temperature ambient temperature electrostatic discharge voltage MM HBM all pins except PILLP, RFIN1, RFIN2 pin PILLP only pins RFIN1 and RFIN2
[1] [2] Machine model I (L = 0.75 mH, R = 10 , C = 200 pF). Human body model (R = 1.5 k, C = 100 pF).
[2] [2] [2] [1]
Conditions
Min -0.3 -0.3 -0.3 -0.3
Max +8 +8 +5.5 +8 +5.5 +150 +85 +200 +2000 +2000 +2000
Unit V V V V V C C V V V V
with respect to ground
-0.3 -55 -40 -200 -2000 -1000 -1500
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13. Static characteristics
Table 45: Characteristics The minimum and maximum values include spread due to VCCA = VCCD = 2.5 V to 3.3 V and Tamb = -20 C to +85 C; unless otherwise specified. Symbol VCCA VCCD VVREFDIG Parameter analog supply voltage digital supply voltage digital reference voltage for I2C-bus interface on pin VREFDIG analog supply current VCCA = 2.5 V to 3.3 V operating mode Standby mode ICCD digital supply current VCCD = 2.5 V to 3.3 V operating mode Standby mode IVREFDIG digital reference supply current operating mode; VVREFDIG = 1.65 V to VCCD 0.3 1 0 0.7 15 0.5 1.5 22.5 1 mA A A 12 0 13.7 0.1 16 1 mA A Conditions Min 2.5 2.5 1.65 Typ 2.7 2.7 1.8 Max 3.3 3.3 VCCD Unit V V V Supply voltages
Supply currents ICCA
DC operating points VLOOPSW VCPOUT VLO1 VLO2 VPILLP VTMUTE VVAFL VVAFR VMPXOUT VMPXIN VFREQIN VXTAL VRFIN1 VRFIN2 VCAGC voltage on pin LOOPSW voltage on pin CPOUT voltage on pin LO1 voltage on pin LO2 voltage on pin PILLP voltage on pin TMUTE voltage on pin VAFL voltage on pin VAFR voltage on pin MPXOUT voltage on pin MPXIN voltage on pin FREQIN voltage on pin XTAL to CD3 voltage on pin RFIN1 voltage on pin RFIN2 voltage on pin CAGC VRF = 0 V VRF = 0 V, measured with respect to pin CD3 fRF = 98 MHz; VRF = 1 mV; no modulation fRF = 98 MHz; VRF = 1 mV; no modulation fRF = 98 MHz; VRF = 1 mV; no modulation fRF = 98 MHz; VRF = 1 mV; no modulation TRIGFR = 1 TRIGFR = 0 TRIGFR = 1 TRIGFR = 0 VCD3 - 0.2 0.1 VCD3 - 0.1 VCD3 - 0.1 1.09 0.6 800 800 830 0.2 1.3 0 0.9 0.8 420 420 1 1.37 0.7 850 850 900 0.4 1.5 0.05 1.17 1 530 530 1.57 VCD3 VCD3 - 0.1 VCD3 VCD3 1.65 0.8 940 940 950 0.5 1.7 0.1 1.3 1.2 680 680 2 V V V V V mV mV mV mV V V V V V mV mV V
TEA5764UK_2
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TEA5764UK
FM radio + RDS
14. Dynamic characteristics
Table 46: Characteristics See Figure 1; all AC values are given in RMS; the minimum and maximum values include spread due to VCCA = VCCD = 2.5 V to 3.3 V and Tamb = -20 C to +85 C; unless otherwise specified. All RF input values are defined in potential difference, except when EMF is explicitly stated. Symbol fosc Ri Ci frsn frsn VIH VIL C/N Parameter oscillator frequency input resistance input capacitance resonance frequency resonance frequency deviation duty cycle HIGH-level input voltage LOW-level input voltage carrier-to-noise ratio Tamb = 25 C Tamb = -20 C to +85 C square wave square wave square wave at 10 kHz Conditions Min 150 500 5 -20 -150 30 1.15 0 -151 Typ 6 32.768 Max 217 7 +20 +150 70 VCC 0.55 Unit MHz k pF kHz ppm ppm % V V dBc/ Hz kHz ppm pF fF k Voltage controlled oscillator Reference frequency input; pin FREQIN
Crystal oscillator 32.768 kHz; pin XTAL frsn frsn Cshunt Cm Rs resonance frequency resonance frequency deviation shunt capacitance motional capacitance series resistance Tamb = 25 C -20 1.5 32.768 +20 3.5 3.0 75
Synthesizer Programmable divider D/Dprog programmable divider ratio FRQSETMSB[15:8] = XX11 1111; FRQSETLSB[7:0] = 1111 1110 FRQSETMSB[15:8] = XX00 1000; FRQSETLSB[7:0] = 0000 0000 Dstep(prog) IM(sink) IM(source) IF counter N Vsens ncount T fres
TEA5764UK_2
-
-
8191
2048
-
-
programmable divider step size peak sink current peak source current length sensitivity voltage count result for search stop period frequency resolution 10 V < VRF < 1 V IFCTC = 1 IFCTC = 0
250 250 31 -
1 500 500 7 5.5 15625 1953 4096
1000 1000 15 3C nA nA bit V Hex s s Hz
Charge pump; pin CPOUT; VLOOPSW = 0.2 V to (VLO2 - 0.2) V; fVCO > fref x divider ratio
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FM radio + RDS
Table 46: Characteristics ...continued See Figure 1; all AC values are given in RMS; the minimum and maximum values include spread due to VCCA = VCCD = 2.5 V to 3.3 V and Tamb = -20 C to +85 C; unless otherwise specified. All RF input values are defined in potential difference, except when EMF is explicitly stated. Symbol Ri VIH VIL VO(max) VO(min) Isink(max) IL(max) Parameter input resistance HIGH-level input voltage LOW-level input voltage maximum output voltage minimum output voltage maximum sink current maximum leakage current VSWPORT = 0 V to 5 V input switching level up input switching level down Iload = 150 A Iload = 150 A Conditions Min 10 Typ Max VVREFDIG + 0.3 Unit M V Logic pins; pins BUSENABLE, SCL and SDA 0.7VVREFDIG -0.3 VVREFDIG - 0.2 0 400 500 -1.0 -
0.3VVREFDIG V VVREFDIG 0.2 2000 1100 +1.0 V V A A A
Software programmable port; pin SWPORT
Isource(max) maximum source current
Interrupt flag; pin INTX; VVREFDIG = 1.65 V to 1.95 V; Iload(max) = 200 A or Rpu of second device connected to pin INTX is 18 k 20 % VO(max) VO(min) Ipd Rpu tL maximum output voltage minimum output voltage pull-down current pull-up resistance LOW time one-shot pulse time VVREFDIG - 0.2 0.130 500 14.4 9.9 0.215 680 18 9.98 VVREFDIG 0.4 1200 22.5 10 V V A k ms
Table 47: FM signal channel characteristics See Figure 1; all AC values are given in RMS; the min. and max. values include spread due to VCCA = VCCD = 2.5 V to 3.3 V and Tamb = -20 C to +85 C; unless otherwise specified. All RF input values are defined in potential difference, except when EMF is explicitly stated. Symbol Ri Ci Vsens(EMF) Parameter input resistance input capacitance sensitivity EMF value voltage Conditions connected to pin GNDRF connected to pin GNDRF fRF = 76 MHz to 108 MHz; f = 22.5 kHz; fmod = 1 kHz; (S+N)/N = 26 dB; TCdeem= 75 s; A-weighting filter; Baud = 300 Hz to 15 kHz f1 = 200 kHz; f2 = 400 kHz; ftune = 76 MHz to 108 MHz; RFagc = off f1 = 4 MHz; f2 = 8 MHz; ftune = 76 MHz to 108 MHz; RFagc = off fRF = 98 MHz; Vth(mute) / Vsens(EMF) < 4 mV/dBV Min 75 2.5 Typ 100 4 2.9 Max Unit 125 6 4.4 pF V FM RF input; pins RFIN1 and RFIN2
IP3in IP3out In-band AGC Vi(AGC)(min)
in-band 3rd-order intercept point out-of-band 3rd-order intercept point minimum RF AGC input voltage
78 87
87 93
-
dBV dBV
55
61
67
dBV
TEA5764UK_2
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FM radio + RDS
Table 47: FM signal channel characteristics ...continued See Figure 1; all AC values are given in RMS; the min. and max. values include spread due to VCCA = VCCD = 2.5 V to 3.3 V and Tamb = -20 C to +85 C; unless otherwise specified. All RF input values are defined in potential difference, except when EMF is explicitly stated. Symbol Wideband AGC Vi(RF) RF input voltage fRF = 93 MHz; fRF2 = 98 MHz; VRF2 = 50 dBV; Vth(mute) / Vsens(EMF) < 4 mV/dBV; radio tuned to 98 MHz 66 72 78 dBV Parameter Conditions Min Typ Max Unit
IF filter fcenter B S center frequency bandwidth selectivity ftune = 76 MHz to 108 MHz high-side; f = +200 kHz low-side; f = -200 kHz high-side; f = +100 kHz low-side; f = -100 kHz IR image rejection ftune = 76 MHz to 108 MHz; VRF = 50 dBV VRF = 0 V VRF = 3 V VIF(slope) VADC(start) Gstep RTMUTE Vo slope of IF voltage level ADC start voltage step resolution gain pin TMUTE output resistance output voltage VRF = 1 mV; L = R; f = 22.5 kHz; fmod = 1 kHz; DTC = 0; Baud = 300 Hz to 15 kHz Vlevel / VRF; VRF = 10 V to 500 V
[1]
215 85 39 32 8 8 24
225 94 43 36 12 12 30
235 102 -
kHz kHz dB dB dB dB dB
FM IF level detector and mute voltage VIF IF voltage 1.5 1.6 130 2 2 280 55 1.55 1.6 1.61 1.7 170 3 3 400 70 210 5 5 520 75 V V mV/20dB V dB k mV
FM demodulator
Ro Isink (S+N)/N
output resistance sink current maximum signal-to-noise ratio fRF = 76 MHz to 108 MHz; VRF = 1 mV; L = R; f = 22.5 kHz; fmod = 1 kHz; TCdeem= 75 s; A-weighting filter; Baud = 300 Hz to 15 kHz total harmonic distortion VRF = 1 mV; L = R; f = 75 kHz; fmod = 1 kHz; DTC = 0; A-weighting filter; Baud = 300 Hz to 15 kHz; see Figure 17 VRF = 1 mV; L = R; f = 100 kHz; fmod = 1 kHz; DTC = 0; A-weighting filter; Baud = 300 Hz to 15 kHz; see Figure 17 L = R; f = 22.5 kHz; fmod = 1 kHz; VRF = 100 V to 10 mV; m = 0.3; DTC = 0; Baud = 300 Hz to 15 kHz
30 54
57
500 -
A dB
THD
-
0.4
0.9
%
THDOD
total harmonic distortion overdrive
-
-
1
%
AMsup
AM suppression
-40
-
-
dB
TEA5764UK_2
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FM radio + RDS
Table 47: FM signal channel characteristics ...continued See Figure 1; all AC values are given in RMS; the min. and max. values include spread due to VCCA = VCCD = 2.5 V to 3.3 V and Tamb = -20 C to +85 C; unless otherwise specified. All RF input values are defined in potential difference, except when EMF is explicitly stated. Symbol Vstart(mute) mute MPX decoder VVAFL left audio output voltage on pin VRF = 1 mV; L = R; f = 22.5 kHz; VAFL fmod = 1 kHz; no pre-emphasis; TCdeem = 75 s right audio output voltage on pin VAFR output resistance pin VAFL VRF = 1 mV; L = R; f = 22.5 kHz; fmod = 1 kHz; no pre-emphasis; TCdeem = 75 s RDSCDA = 0 MU = LHM = RHM = 0 MU = LHM = RHM = 1 RVAFR output resistance pin VAFR RDSCDA = 0 MU = LHM = RHM = 0 MU = LHM = RHM = 1 Isink(VAFL) Isink(VAFR) ODi sink current on pin VAFL sink current on pin VAFR input overdrive range THD = 3 % relative to fMPX = 1 kHz; VMPX = 250 mV 50 500 200 200 4 100 300 300 k A A dB 50 500 100 k 55 66 75 mV Parameter mute start voltage mute attenuation Conditions relative to VVAFL at VRF = 1 mV; mute = 3 dB VRF = 1 V; L = R; DTC = 0; Baud = 300 Hz to 15 kHz Min 3 10 Typ 5 20 Max Unit 10 30 V dB Soft mute; SMUTE = 1; f = 22.5 kHz; fmod = 1 kHz
VVAFR
55
66
75
mV
RVAFL
VRF = 1 mV; L = R; f = 75 kHz VO(VAFL-VAFR) output voltage difference between pins VAFL and VAFR including 9 % pilot deviation; fmod = 1 kHz cs channel separation VRF = 1 mV; f = 75 kHz including 9 % pilot deviation; R = 1; L = 0 or R = 0; L = 1; fmod = 1 kHz; MST = 0; SNC = 1; Baud = 300 Hz to 15 kHz VRF = 1 mV; f = 22.5 kHz; pre-emphasis = 75 s; DTC = 0; L = R; with C between pin 27 and pin 26 = 33 nF 5 %
-0.5 -
+0.5 dB
27
-
-
dB
fu fl
upper 3 dB bandwidth lower 3 dB bandwidth
13 20
15 30
17 50
kHz Hz
(S+N)/N(m)
maximum signal-to-noise ratio, VRF = 1 mV; f = 22.5 kHz; L = R; fmod = 1 kHz; de-emphasis = 75 s; mono BAF = 300 Hz to 15 kHz; A-weighting filter maximum signal-to-noise ratio, VRF = 1 mV; f = 67.5 kHz; L = R; stereo fmod = 1 kHz; fpilot = 6.75 kHz; de-emphasis = 75 s; BAF = 300 Hz to 15 kHz; A-weighting filter
54
57
-
dB
(S+N)/N(s)
50
54
-
dB
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FM radio + RDS
Table 47: FM signal channel characteristics ...continued See Figure 1; all AC values are given in RMS; the min. and max. values include spread due to VCCA = VCCD = 2.5 V to 3.3 V and Tamb = -20 C to +85 C; unless otherwise specified. All RF input values are defined in potential difference, except when EMF is explicitly stated. Symbol THD Parameter total harmonic distortion Conditions VRF = 1 mV; L = 1; R = 0; f = 75 kHz including 9 % pilot deviation; fmod = 1 kHz; DTC = 0; Baud = 300 Hz to 15 kHz; A-weighting filter mono; L = R; no pilot deviation stereo; L = 1, R = 0; 9 % pilot deviation; see Figure 17 sup(pilot) pilot suppression measured at pins VAFL and VAFR; related to f = 75 kHz including 9 % pilot deviation; fmod = 1 kHz; DTC = 0 VRF = 1 mV VRF = 1 mV VRF = 1 mV DTC = 1 DTC = 0 Mono stereo blend; SNC = 1 Vstart(blend) cs blend start voltage channel separation cs = 0.5 dB VRF = 30 V; f = 75 kHz including 9 % pilot deviation; R = 1 and L = 0 or R = 0 and L = 1; fmod = 1 kHz; MST = 0; SNC = 1 MST = 0; R = 1 and L = 0 or R = 0 and L=1 VRF = 30 V; increasing RF input level VRF = 10 V; decreasing RF input level Vsw hys switching voltage hysteresis
[4] [4] [3]
Min
Typ
Max Unit
40
0.4 0.9 50
0.9 2.5 -
% % dB
fpilot hys(pilot) TCdeem
pilot frequency deviation pilot tone detection hysteresis de-emphasis time constant
Table note [2] 2 38 57 2 4 50 75 7 10 6 62 93 15 16 dB s s V dB
Mono stereo switching; f = 75 kHz including 9 % pilot deviation; fmod = 1 kHz; SNC = 0 cs channel separation
27 17 3
33 25 3.5
1 45 4
dB dB V dB
Bus driven mute functions Tuning mute; AFM = 1 mute(VAFR) mute depth on pin VAFR AFM = 1 or RHM = 1; f = 75 kHz; mono; Baud = 300 Hz to 15 kHz; A-weighting filter AFM = 1 or LHM = 1; f = 75 kHz; mono; Baud = 300 Hz to 15 kHz; A-weighting filter MU = 1; f = 75 kHz; mono; Baud = 300 Hz to 15 kHz; A-weighting filter -60 dB
mute(VAFL)
mute depth on pin VAFL
-60
-
-
dB
mute
mute depth on pins VAFL and VAFR
-80
-
-
dB
TEA5764UK_2
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FM radio + RDS
Table 47: FM signal channel characteristics ...continued See Figure 1; all AC values are given in RMS; the min. and max. values include spread due to VCCA = VCCD = 2.5 V to 3.3 V and Tamb = -20 C to +85 C; unless otherwise specified. All RF input values are defined in potential difference, except when EMF is explicitly stated. Symbol Parameter Conditions Min Typ Max Unit RDS demodulator/decoder; f = 22.5 kHz; fAF = 1 kHz; L = R; TCdeem = 50 s; DTC = 1; SYM1 = 0 and SYM0 = 0; average over 2000 blocks IRDS Vsens RDS current RDS sensitivity EMF value ICCD current when RDS is running f = 22.5 kHz; fAF = 1 kHz; L = R; SYM1 = 0 and SYM0 = 0 block quality rate 85 %; fRDS = 1.2 kHz block quality rate 95 %; fRDS = 2 kHz fcenter B Pause detector fth(det)(pause) pause detection threshold frequency fmod = 1 kHz; L = R; PL0 = 0; PL1 = 0 0.7 1.0 1.4 kHz filter center frequency bandwidth 24.7 37.5 V 17 30 V 0.3 0.7 1.5 mA
56.5 57 2.5 3
57.5 kHz 3.5 kHz
[1] [2] [3] [4]
Low-side and high-side selectivity can be measured by changing the mixer LO injection from high-side to low-side. When bit STEREO is at logic 1 the frequency is between 2.5 kHz and 5.8 kHz; when bit STEREO is at logic 0 the frequency is 0 kHz. With increasing input levels the radio switches gradually from mono to stereo. The mono stereo switching level is the RF input level for switching from mono to stereo.
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FM radio + RDS
0 (dB) -20
001aac797
(1)
4.0 THD, N (%) 3.0
(2)
-40
2.0
-60
(3)
1.0
-80 10-7
10-6
10-5
10-4
10-3
10-2
10-1
0 VRF (V) 1
(1) Mono signal, soft mute off (fFM = 22.5 kHz; fAF = 1 kHz) (2) Noise in mono mode, soft mute off (3) Total harmonic distortion, f = 75 kHz (fFM = 75 kHz; fAF = 1 kHz) VCCA = 2.7 V; Tamb = 25 C; AFout: A-weighting filter, BP filter: 300 Hz to 15 kHz 0 dB = 72 mV at 2 V RF -3 dB = 0.8 V 26 dB = 1.4 V. RF = 98 MHz Measurements/decade: 12
Fig 15. Mono characteristics
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FM radio + RDS
0
(1)
001aac798
4.0 THD, N (%) 3.0
(dB)
(2)
-20
-40
(3)
2.0
-60
(4)
1.0
-80 10-7
10-6
10-5
10-4
10-3
10-2
10-1
0 VRF (V) 1
(1) VAFL signal, soft mute off (fR = 67.5 kHz; fAF = 1 kHz; fpilot = 6.75 kHz) (2) VAFR signal, soft mute off (fL = 67.5 kHz; fAF = 1 kHz; fpilot = 6.75 kHz) (3) Noise in stereo mode, soft mute off (fL = 0 kHz; fAF = 1 kHz; fpilot = 6.75 kHz) (4) Total harmonic distortion, f = 75 kHz (fR = 67.5 kHz; fAF = 1 kHz; fpilot = 6.75 kHz) VCCA = 2.7 V; Tamb = 25 C; AFout: A-weighting filter, BP filter: 300 Hz to 15 kHz; SNC = on 0 dB = 233 mV at 470 V RF 26 dB = 1.3 V RF = 98 MHz Measurements/decade: 12
Fig 16. Stereo characteristics
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FM radio + RDS
0
(1)
001aac799
4.0 THD, N (%) 3.0
(dB) -20
-40
(2)
2.0
-60
(3)
1.0
-80 10-7
10-6
10-5
10-4
10-3
10-2
10-1
0 VRF (V) 1
(1) Mono signal, soft mute on (fFM = 22.5 kHz; fAF = 1 kHz) (2) Noise in mono mode, soft mute on (3) Total harmonic distortion, f = 100 kHz (fFM = 100 kHz; fAF = 1 kHz) VCCA = 2.7 V; Tamb = 25 C; AFout: A-weighting filter, BP filter: 300 Hz to 15 kHz; soft mute on 0 dB = 71 mV at 10 V RF 26 dB = 1.4 V RF = 98 MHz Measurements/decade: 12
Fig 17. Soft mute and overdrive characteristics
10-3 VRFIN1, VRFIN2 (V) 10-4
001aac800
10-5
10-6
10-7 0 4 8 12 ADC output 16
Fig 18. ADC conversion levels
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FM radio + RDS
15. Application information
Table 48: Symbol D1, D2 L1 L2, L3 X1 R C List of components Parameter RF band filter coil VCO coil 32.768 kHz crystal 10 k; 47 k; 100 k 27 pF; 47 pF; 100 pF; 12 pF; 10 nF(2x); 33 nF(8x) Type 120 nH; Qmin = 20; tolerance: 5 % 33 nH; Qmin = 40; tolerance: 2 % Manufacturer Philips Coilcraft; Murata Coilcraft; Murata varicap diode for VCO tuning BB202
ACT200; CL = 12 pF; f / f0 = 20 ppm; ACT see Section 14 10 % max 10 % max
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FM radio + RDS
16. Package outline
WLB34: wafer-level ball grid array; 34 balls; 4 x 4 x 0.36 mm TEA5764UK
D
B A
ball A1 index area
A2 E A A1
detail X
C e1 e b v w
M M
CAB C
y
G F e E D C B A e2
1
2
3
4
5
6 0
7 1 scale 2 3 mm
X
DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.6 A1 0.26 0.22 A2 0.38 0.34 b 0.38 0.28 D 4.02 3.96 E 4.02 3.96 e 0.5 e1 3 e2 3 v 0.05 w 0.1 y 0.015
OUTLINE VERSION TEA5764UK
REFERENCES IEC JEDEC JEITA
EUROPEAN PROJECTION
ISSUE DATE 05-04-21 05-06-23
Fig 19. Package outline TEA5764UK (WLB34)
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17. Soldering
17.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
17.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 225 C (SnPb process) or below 245 C (Pb-free process)
- for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
17.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
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- smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
17.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C.
17.5 Package related soldering information
Table 49: Package [1] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L [8], PMFP [9], WQCCN..L [8]
[1] [2]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable [4] Reflow [2] suitable suitable
suitable not not recommended [5] [6] recommended [7]
suitable suitable suitable not suitable
not suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.
[3]
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FM radio + RDS
[4]
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages.
[5] [6] [7] [8]
[9]
TEA5764UK_2
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 9 August 2005
60 of 64
Philips Semiconductors
TEA5764UK
FM radio + RDS
18. Revision history
Table 50: Revision history Release date 20050809 Data sheet status Product data sheet Preliminary data sheet Change notice Doc. number Supersedes TEA5764UK_1 Document ID TEA5764UK_2 Modifications: TEA5764UK_1
*
Specification status changed from preliminary data sheet to product data sheet.
20050701
TEA5764UK_2
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 9 August 2005
61 of 64
Philips Semiconductors
TEA5764UK
FM radio + RDS
19. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
20. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
22. Trademarks
Notice -- All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- wordmark and logo are trademarks of Koninklijke Philips Electronics N.V.
21. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
23. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
TEA5764UK_2
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 9 August 2005
62 of 64
Philips Semiconductors
TEA5764UK
FM radio + RDS
24. Contents
1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Low noise RF amplifier . . . . . . . . . . . . . . . . . . 6 FM I/Q mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . 6 PLL tuning system . . . . . . . . . . . . . . . . . . . . . . 7 Band limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 RF AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Local or long distance receive . . . . . . . . . . . . . 8 IF filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 FM demodulator . . . . . . . . . . . . . . . . . . . . . . . . 8 IF counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Voltage level generator and analog-to-digital converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.13 Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.13.1 Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.13.2 Hard mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.13.3 Audio frequency mute . . . . . . . . . . . . . . . . . . . . 9 8.14 MPX decoder . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.15 Signal dependent mono/stereo blend (stereo noise cancellation) . . . . . . . . . . . . . . . . . . . . . . 9 8.16 Software programmable port . . . . . . . . . . . . . 10 8.17 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . 10 8.18 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 10 8.19 RDS/RBDS . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8.19.1 RDS/RBDS demodulator . . . . . . . . . . . . . . . . 10 8.19.2 RDS data and clock direct . . . . . . . . . . . . . . . 10 8.19.2.1 RDS/RBDS decoder . . . . . . . . . . . . . . . . . . . . 11 8.20 Audio pause detector . . . . . . . . . . . . . . . . . . . 11 8.21 Auto search and Preset mode . . . . . . . . . . . . 11 8.21.1 Search mode . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.21.2 Preset mode . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.21.3 Auto high-side and low-side injection stop switch . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.21.4 Muting during search or preset . . . . . . . . . . . . 14 8.22 RDS update/alternative frequency jump . . . . . 14 8.22.1 Muting during RDS update . . . . . . . . . . . . . . . 15 9 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . 9.1 Interrupt register. . . . . . . . . . . . . . . . . . . . . . . 9.1.1 Interrupt clearing . . . . . . . . . . . . . . . . . . . . . . 9.1.2 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.4 Interrupt flags and behavior . . . . . . . . . . . . . . 9.1.4.1 Multiple interrupt events . . . . . . . . . . . . . . . . . 9.1.4.2 Data available flag . . . . . . . . . . . . . . . . . . . . . 9.1.4.3 RDS synchronization flag. . . . . . . . . . . . . . . . 9.1.4.4 IF frequency flag . . . . . . . . . . . . . . . . . . . . . . 9.1.4.5 RSSI threshold flag . . . . . . . . . . . . . . . . . . . . 9.1.4.6 Pause detection flag. . . . . . . . . . . . . . . . . . . . 9.1.4.7 Frequency ready flag . . . . . . . . . . . . . . . . . . . 9.1.4.8 Band limit flag. . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Interrupt output. . . . . . . . . . . . . . . . . . . . . . . . 10 RDS data processing . . . . . . . . . . . . . . . . . . . 10.1 DAV-A processing mode. . . . . . . . . . . . . . . . . 10.2 DAV-B processing mode / fast PI search mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 DAV-C reduced processing mode . . . . . . . . . 10.4 Synchronization . . . . . . . . . . . . . . . . . . . . . . . 10.4.1 Conditions for synchronization . . . . . . . . . . . . 10.4.2 Data overflow . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 RDS flag behavior during read action . . . . . . 10.6 Error detection and reporting . . . . . . . . . . . . . 10.7 RDS test modes . . . . . . . . . . . . . . . . . . . . . . . 10.8 Reading RDS data from the registers . . . . . . 11 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 11.1 Write and read mode . . . . . . . . . . . . . . . . . . . 11.2 Data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 Register map . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 Byte description . . . . . . . . . . . . . . . . . . . . . . . 12 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 13 Static characteristics . . . . . . . . . . . . . . . . . . . 14 Dynamic characteristics . . . . . . . . . . . . . . . . . 15 Application information . . . . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.1 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . 17.2 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 17.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 17.4 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 17.5 Package related soldering information . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . 19 Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 16 16 17 17 17 19 19 19 19 20 20 21 22 23 23 23 24 25 26 28 28 29 30 31 31 31 31 31 32 34 34 45 46 47 56 57 58 58 58 58 59 59 61 62
continued >>
TEA5764UK_2
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 9 August 2005
63 of 64
Philips Semiconductors
TEA5764UK
FM radio + RDS
62 62 62 62
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Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . .
(c) Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 9 August 2005 Document number: TEA5764UK_2
Published in The Netherlands

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